MOS(metal oxide silicon) controlled thyristor device

Patent metadata

Field	Value
Publication number	US-11784247-B2
Application number	US-202117792070-A
Country	US
Kind code	B2
Filing date	Jun 10, 2021
Priority date	Jun 10, 2020
Publication date	Oct 10, 2023
Grant date	Oct 10, 2023

Abstract

A MOS controlled thyristor device according to the concept of the present invention includes a substrate comprising a first surface and a second surface, which face each other, gate patterns disposed on the first surface, a cathode electrode configured to cover the gate patterns, and an anode electrode disposed on the second surface, The substrate includes a lower emitter layer having a first conductive type, a lower base layer having a second conductive type on the lower emitter layer, an upper base region provided in an upper portion of the lower emitter layer and having a first conductive type, wherein the upper base region is configured to expose a portion of a top surface of the lower base layer, an upper emitter region having a second conductive type and provided in an upper portion of the upper base region, a first doped region having a first conductive type and a second doped region surrounded by the first doped region and having a second conductive type, wherein the first and second doped regions are provided in an upper portion of the upper emitter region, and a first doping pattern having a first conductive type, which is provided on one surface of the upper portion of the upper emitter region. The first doping pattern is interposed between the upper base region and the first doped region along a first direction parallel to the top surface of the substrate. The first doping pattern is configured to expose a top surface of the upper emitter region on the other surface of the upper portion of the upper emitter region. Each of the gate patterns is configured to cover portions of an exposed top surface of the lower base layer, an exposed top surface of the upper base layer, an exposed top surface of the upper emitter region, a top surface of the first doping pattern, and a top surface of the first doped region. The cathode electrode is configured to cover portions of top and side surfaces of the gate pattern, a top surface of the second doped region, and a top surface of the first doped region. The first conductive type and the second conductive type are different from each other.

First claim

The invention claimed is:

1. A MOS controlled thyristor device, comprising:
a substrate ( 100 ) comprising a first surface ( 100 a ) and a second surface ( 100 b ), which face each other;
gate patterns ( 109 ) disposed on the first surface ( 100 a );
a cathode electrode ( 114 ) configured to cover the gate patterns ( 109 ); and
an anode electrode ( 115 ) disposed on the second surface ( 100 b ),
wherein the substrate ( 100 ) comprises:
a lower emitter layer ( 101 ) having a first conductive type;
a lower base layer ( 103 ) having a second conductive type on the lower emitter layer ( 101 );
an upper base region ( 104 ) provided in an upper portion of the lower emitter layer ( 101 ) and having a first conductive type, wherein the upper base region ( 104 ) is configured to expose a portion of a top surface of the lower base layer ( 103 );
an upper emitter region ( 105 ) having a second conductive type and provided in an upper portion of the upper base region ( 104 );
a first doped region ( 106 ) having a first conductive type and a second doped region ( 107 ) surrounded by the first doped region ( 106 ) and having a second conductive type, wherein the first and second doped regions ( 106 , 107 ) are provided in an upper portion of the upper emitter region ( 105 ); and
a first doping pattern ( 110 ) having a first conductive type, which is provided on one surface of the upper portion of the upper emitter region ( 105 ),
wherein the first doping pattern ( 110 ) is interposed between the upper base region ( 104 ) and the first doped region ( 106 ) along a first direction (D 1 ) parallel to the top surface ( 100 a ) of the substrate,
the first doping pattern ( 110 ) is configured to expose a top surface ( 111 ) of the upper emitter region ( 105 ) on the other surface of the upper portion of the upper emitter region ( 105 ),
each of the gate patterns ( 109 ) is configured to cover portions of an exposed top surface of the lower base layer ( 103 ), an exposed top surface ( 112 ) of the upper base layer ( 104 ), an exposed top surface ( 111 ) of the upper emitter region ( 105 ), a top surface of the first doping pattern ( 110 ), and a top surface of the first doped region ( 106 ),
the cathode electrode ( 114 ) is configured to cover portions of top and side surfaces of the gate pattern ( 109 ), a top surface of the second doped region ( 107 ), and a top surface of the first doped region ( 106 ), and
the first conductive type and the second conductive type are different from each other.

2. The MOS controlled thyristor device of claim 1 , wherein the first doping pattern ( 110 ) has a segmented ring or line shape,
the top surface ( 111 ) of the top upper emitter region ( 105 ) is exposed by the segmented portion, and
an area of the top surface of the first doping pattern ( 110 ) is greater than that of a portion of the top surface ( 111 ) of the upper emitter region.

3. The MOS controlled thyristor device of claim 1 , wherein the first doping pattern is disposed adjacent to one surface of the upper emitter region ( 105 ), and
the MOS controlled thyristor device further comprises a second doping pattern having a second conductive type and disposed on the exposed top surface ( 111 ) of the upper emitter region ( 105 ).

4. The MOS controlled thyristor device of claim 3 , wherein the first doping pattern has a segmented ring or segmented line shape,
the second doping pattern ( 116 ) is disposed on the segmented portion, and
an area of the top surface of the first doping pattern is greater than that of a top surface of the second doping pattern ( 116 ).

5. The MOS controlled thyristor device of claim 1 , further comprising a threshold voltage control layer ( 117 ) having a first conductive type and provided in at least a portion of the upper portion of the upper base region ( 104 ),
wherein the threshold voltage control layer ( 117 ) is in contact with the first doping pattern ( 110 ).

6. The MOS controlled thyristor device of claim 5 , wherein the threshold voltage control layer ( 117 ) is disposed over the entire first surface ( 100 a ) of the substrate ( 100 ), and
a doping concentration of each of the first doped region ( 106 ) and the second doped region ( 107 ) is higher than that of the threshold voltage control layer ( 117 ).

7. The MOS controlled thyristor device of claim 5 , wherein the first doping pattern ( 110 ) is disposed adjacent to one surface of the upper emitter region ( 105 ),
the MOS controlled thyristor device further comprises a second doping pattern ( 116 ) having a second conductive type and disposed on the other surface of the upper emitter region ( 105 ), and
the threshold voltage control layer ( 117 ) is in contact with the first doping pattern ( 110 ) and the second doping pattern ( 116 ).

8. The MOS controlled thyristor device of claim 5 , wherein the threshold voltage control layer ( 117 ) is disposed over the entire first surface ( 100 a ) of the substrate ( 100 ), and
a doping concentration of each of the first doped region ( 106 ), the second doped region ( 107 ), and the second doping pattern ( 116 ) is higher than that of the threshold voltage control layer ( 117 ).

9. The MOS controlled thyristor device of claim 1 , wherein the upper emitter region ( 105 ) is provided in plurality,
the upper emitting regions ( 105 ) are spaced apart from each other along the first direction (D 1 ),
each of the upper emitter regions ( 105 ) is parallel to the first surface ( 100 a ) of the substrate ( 100 ) and extends along a second direction (D 2 ) crossing the first direction (D 1 ), and the first doped region ( 106 ) is provided in a pair within the upper emitter region ( 105 ),
the pair of first doped regions ( 106 ) are spaced apart from each other with the second doped region ( 107 ) therebetween,
each of the first doped regions ( 106 ) and the second doped region ( 107 ) extend in a line shape along the second direction (D 2 ), and
the exposed top surface ( 111 ) of the upper emitter region ( 105 ) and the first doping pattern ( 110 ) are spaced apart from each other with the pair of doped regions ( 106 ) and the second doped region ( 107 ) therebetween in the first direction (D 1 ).

10. The MOS controlled thyristor device of claim 9 , wherein the first doping pattern ( 110 ) has a segmented line shape, the top surface ( 111 ) of the upper emitter region ( 105 ) is exposed at the segmented portion.

11. The MOS controlled thyristor device of claim 9 , wherein the first doping pattern ( 111 ) has a segmented line shape, and
the MOS controlled thyristor device further comprises a second doping pattern ( 116 ) provided at the segmented portion.

12. The MOS controlled thyristor device of claim 1 , wherein the upper emitter region ( 105 ) is provided in plurality, and
in view of planarity,
the upper emitter regions ( 105 ) are arranged to be spaced apart from each other along the first direction (D 1 ) and a second direction (D 2 ), wherein the second direction (D 2 ) is parallel to the first surface ( 100 a ) of the substrate ( 100 ) and crosses the first direction (D 1 ),
the second doped region ( 107 ) has a circular shape,
the first doped region ( 106 ) has a ring shape, and
the first doping pattern ( 110 ) has a segmented ring shape that surrounds the first doped region ( 106 ).

13. The MOS controlled thyristor device of claim 12 , wherein each of the first doping pattern ( 110 ) and the exposed top surface ( 111 ) of the upper emitter region ( 105 ) is spaced apart from the exposed top surface of the lower base layer ( 103 ) with the exposed top surface ( 112 ) of the upper b

Assignees

• Electronics & Telecommunications Res Inst

Inventors

• Park Kun Sik
• Won Jong Il
• Cho Doo Hyung
• Jung Dong Yun
• Jang Hyun Gyu

Classifications

• H10D84/0105

  the built-in components being field-effect devices · CPC title

• H10D62/192

  Base regions of thyristors · CPC title

• H10D62/148

  Cathode regions of thyristors · CPC title

• H10D18/40

  with turn-on by field effect · CPC title

• H10D62/127

  of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs · CPC title