Profile shaping for control gate recesses

Patent metadata

Field	Value
Publication number	US-11784229-B2
Application number	US-202017073060-A
Country	US
Kind code	B2
Filing date	Oct 16, 2020
Priority date	Oct 16, 2020
Publication date	Oct 10, 2023
Grant date	Oct 10, 2023

Abstract

Exemplary semiconductor structures and processing methods may include forming a first portion of a first semiconductor layer characterized by a first etch rate for an etch treatment, forming a second portion of the first semiconductor layer characterized by a second etch rate that is less than the first etch rate for the etch treatment, and forming a third portion of the first semiconductor layer characterized by a third etch rate that is greater than the second etch rate. The processing methods may further include etching an opening through the first semiconductor layer, where the opening has a height and a width, and where the opening is characterized by a variation in the width between a midpoint of the height of the opening and an endpoint of the opening that is less than or about 5 Å.

First claim

The invention claimed is:

1. A semiconductor processing method comprising:
forming a first portion of a first semiconductor layer characterized by a first etch rate for an etch treatment;
forming a second portion of the first semiconductor layer characterized by a second etch rate that is less than the first etch rate for the etch treatment;
forming a third portion of the first semiconductor layer characterized by a third etch rate that is greater than the second etch rate; and
etching an opening through the first semiconductor layer, wherein the opening has a height and a width, and wherein the opening is characterized by a variation in the width between a midpoint of the height of the opening and an endpoint of the opening that is less than or about 5 Å,
wherein the first semiconductor layer is formed between two dielectric layers.

2. The semiconductor processing method of claim 1 , wherein the first semiconductor layer comprises polysilicon.

3. The semiconductor processing method of claim 1 , wherein the dielectric layers comprise silicon oxide.

4. The semiconductor processing method of claim 1 , wherein the second portion of the first semiconductor layer has a greater atomic percentage of phosphorous than the first portion or third portion of the semiconductor layer.

5. The semiconductor processing method of claim 1 , wherein the second portion of the first semiconductor layer has a higher amount of stress than the first portion or third portion of the semiconductor layer.

6. The semiconductor processing method of claim 1 , wherein the processing method further comprises forming a second semiconductor layer after the formation of the first semiconductor layer, wherein the second semiconductor layer has an average etch rate for the etch treatment that is less than an average etch rate of the first semiconductor layer.

7. The semiconductor processing method of claim 6 , wherein the second semiconductor layer comprises at least three portions that have different etch rates for the etch treatment.

8. A semiconductor processing method comprising:
flowing deposition precursors into a substrate processing region of a semiconductor processing chamber, wherein the deposition precursors comprise a silicon-containing precursor and a doping precursor;
depositing a first portion of a doped polysilicon layer on a substrate in the substrate processing region of the semiconductor processing chamber;
increasing a flow rate ratio of the doping precursor to the silicon-containing precursor and depositing a second portion of the doped polysilicon layer on the substrate, wherein the second portion of the polysilicon layer is characterized by a lower etch rate for an etch treatment than the first portion of the doped polysilicon layer; and
decreasing a flow rate ratio of the doping precursor to the silicon-containing precursor and depositing a third portion of the doped polysilicon layer on the substrate, wherein the third portion of the polysilicon layer is characterized by a higher etch rate for the etch treatment than the second portion of the doped polysilicon layer,
wherein the substrate comprises a first dielectric layer upon which the first portion of the doped polysilicon layer is deposited and the doping precursor comprises a phosphorous-containing precursor.

9. The semiconductor processing method of claim 8 , wherein the silicon-containing precursor comprises silane.

10. The semiconductor processing method of claim 8 , wherein the method further comprises etching an opening through the doped polysilicon layer, wherein the opening has a height and a width, and wherein the opening is characterized by a variation in the width between a midpoint of the height of the opening and an endpoint of the opening that is less than or about 5 Å.

11. The semiconductor processing method of claim 8 , wherein the method further comprises depositing a second dielectric layer on the doped polysilicon layer.

Assignees

• Applied Materials Inc

Inventors

• Singhal Akhil
• Yau Allison
• Kim Sang-Jin
• Zhao Zeqiong
• Jiang Zhijun
• Padhi Deenesh
• Balasubramanian Ganesh

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P50/268

  of silicon-containing layers · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10D64/037

  comprising charge-trapping insulators · CPC title

• H10D64/035 Primary

  comprising conductor-insulator-conductor-insulator-semiconductor structures · CPC title