Array substrate, manufacturing method thereof, and display device

Patent metadata

Field	Value
Publication number	US-11784191-B2
Application number	US-202017045187-A
Country	US
Kind code	B2
Filing date	Aug 12, 2020
Priority date	Jun 8, 2020
Publication date	Oct 10, 2023
Grant date	Oct 10, 2023

Abstract

The present disclosure provides an array substrate, a manufacturing method thereof, and a display device. The array substrate includes a substrate, at least one first thin film transistor, and at least one second thin film transistor. A second etching barrier block is disposed between an active layer and a first source electrode, and the first drain electrode is close to the active layer, thereby shortening an effective channel of the first thin film transistor, so that a mobility of transistors and a number of pixels of a panel can be improved.

First claim

What is claimed is:

1. An array substrate, comprising:
a substrate; and
at least one first thin film transistor and at least one second thin film transistor disposed in parallel on the substrate, wherein the first thin film transistor is an oxide thin film transistor, and the second thin film transistor is a low temperature polysilicon (LTPS) thin film transistor; and
wherein the first thin film transistor comprises:
a first gate electrode disposed on the substrate;
a gate insulating layer disposed on the first gate electrode and the substrate;
an active layer disposed on the gate insulating layer;
a first drain electrode disposed on the gate insulating layer, wherein the first drain electrode and the active layer are disposed in a same layer;
a first etching barrier block disposed on the gate insulating layer, wherein the first etching barrier block is located between the second thin film transistor and the first drain electrode; and
a first source electrode disposed on the active layer;
wherein the first drain electrode is connected to and is in contact with a side surface of the active layer, and materials of the first drain electrode and materials of the active layer are indium gallium zinc oxides.

2. The array substrate in claim 1 , comprising:
a passivation layer disposed on the first thin film transistor and the second thin film transistor; and
a first electrode disposed on the passivation layer and connected to the second thin film transistor.

3. The array substrate in claim 1 , wherein the first thin film transistor comprises a second etching barrier block disposed between the active layer and the first source electrode.

4. The array substrate in claim 3 , wherein the second etching barrier block and the first etching barrier block are disposed in a same layer.

5. The array substrate in claim 3 , wherein the second etching barrier block covers a portion of the active layer, a portion of the second etching barrier block is covered by the first source electrode, and the first source electrode forms a stepped structure at the second etching barrier block.

6. The array substrate in claim 1 , wherein the second thin film transistor comprises:
a second gate electrode disposed on the substrate and coated by the gate insulating layer, wherein the second gate electrode and the first gate electrode are disposed in a same layer;
a polysilicon layer disposed on the gate insulating layer;
a second source electrode disposed on the first etching barrier block and the polysilicon layer; and
a second drain electrode disposed on the polysilicon layer.

7. The array substrate in claim 6 , wherein the second source electrode, the second drain electrode, and the first source electrode are disposed in a same layer.

8. The array substrate in claim 6 , wherein an opening is defined in the gate insulating layer and extends downwards to a surface of the second gate electrode, and the active layer is connected to the second gate electrode through the opening.

9. The array substrate in claim 6 , wherein a portion of the second source electrode covers a portion of the first etching barrier block.

10. A manufacturing method of an array substrate, comprising:
providing a substrate;
forming a first gate electrode and a second gate electrode on the substrate;
forming a gate insulating layer on the first gate electrode, the second gate electrode, and the substrate;
forming an active layer, a first drain electrode, and a polysilicon layer on the gate insulating layer;
forming a first etching barrier block on the gate insulating layer and forming a second etching barrier block on the active layer, wherein the first etching barrier block is disposed between the polysilicon layer and the first drain electrode; and
forming a first source electrode on the active layer, forming a second source electrode on the first etching barrier block and the polysilicon layer, and forming a second drain electrode on the polysilicon layer;
wherein the first drain electrode is connected to and is in contact with a side surface of the active layer, and materials of the first drain electrode and materials of the active layer are indium gallium zinc oxides.

11. The manufacturing method of the array substrate in claim 10 , wherein the step of forming the active layer, the first drain electrode, and the polysilicon layer on the gate insulating layer specifically comprises:
forming a semiconductor layer on the gate insulating layer;
after forming a first single crystalline silicon layer on the semiconductor layer, forming the active layer and the first drain electrode by the semiconductor layer, forming a second single crystalline silicon layer on the gate insulating layer, and forming an inducing layer on the second single crystalline silicon layer;
processing the active layer and the second single crystalline silicon layer by a high temperature annealing process, so as to form the polysilicon layer by the second single crystalline silicon layer; and
removing the inducing layer and the first single crystalline silicon layer.

12. A display device, comprising an array substrate, the array substrate comprising:
a substrate; and
at least one first thin film transistor and at least one second thin film transistor disposed in parallel on the substrate, wherein the first thin film transistor is an oxide thin film transistor, and the second thin film transistor is a low temperature polysilicon (LTPS) thin film transistor; and
wherein the first thin film transistor comprises:
a first gate electrode disposed on the substrate;
a gate insulating layer disposed on the first gate electrode and the substrate;
an active layer disposed on the gate insulating layer;
a first drain electrode disposed on the gate insulating layer, wherein the first drain electrode and the active layer are disposed in a same layer;
a first etching barrier block disposed on the gate insulating layer, wherein the first etching barrier block is located between the second thin film transistor and the first drain electrode; and
a first source electrode disposed on the active layer;
wherein the first drain electrode is connected to and is in contact with a side surface of the active layer, and materials of the first drain electrode and materials of the active layer are indium gallium zinc oxides.

13. The display device in claim 12 , wherein the array substrate comprises:
a passivation layer disposed on the first thin film transistor and the second thin film transistor; and
a first electrode disposed on the passivation layer and connected to the second thin film transistor.

14. The display device in claim 12 , wherein the first thin film transistor comprises a second etching barrier block disposed between the active layer and the first source electrode.

15. The display device in claim 14 , wherein the second etching barrier block and the first etching barrier block are disposed in a same layer.

16. The display device in claim 12 , wherein the second thin film transistor comprises:
a second gate electrode disposed on the substrate and coated by the gate insulating layer, wherein the second gate electrode and the first gate electrode are disposed in a same layer;
a polysilicon layer disposed on the gate insulating layer;
a second source electrode disposed on the first etching barrier block and the polysilicon layer; and
a second drain electrode disposed on the polysilicon layer.

17. The display device in claim 16 , wherein the second source electrode, the second drain electrode and the first source electrode are d

Assignees

• Tcl China Star Optoelectronics Tech Co Ltd

Inventors

• Li Jinming

Classifications

• H10D86/423 Primary

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D86/0223

  comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials · CPC title

• H10D86/431

  having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title