Encapsulated device of semiconductor material with reduced sensitivity to thermo-mechanical stresses
US-2017088416-A1 · Mar 30, 2017 · US
US11780727B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11780727-B2 |
| Application number | US-202117295598-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 12, 2021 |
| Priority date | Sep 22, 2020 |
| Publication date | Oct 10, 2023 |
| Grant date | Oct 10, 2023 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A low-stress packaging structure for a MEMS acceleration sensor chip includes a MEMS sensor chip and a chip carrier. Two sides of the bottom of the sensor chip are provided with a first metal layer and a second metal layer respectively. Two sides of a die attach area of the chip carrier are correspondingly provided with a third metal layer and a fourth metal layer. The first metal layer of the sensor chip and the third metal layer of the chip carrier are bonded together. The second metal layer of the sensor chip and the fourth metal layer of the chip carrier are only in contact but not bonded. A groove is arranged between the first metal layer and the second metal layer at the bottom of the sensor chip. A certain gap is defined between the sensor chip and cavity walls of chip carrier.
Opening claim text (preview).
What is claimed is: 1. A low-stress packaging structure, comprising: a MEMS acceleration sensor chip, wherein two sides of the bottom of the MEMS acceleration sensor chip are provided with a first metal layer and a second metal layer respectively, and a groove is arranged between the first metal layer and the second metal layer and close to the first metal layer; and a chip carrier, wherein two sides of a die attach area of the chip carrier are correspondingly provided with a third metal layer and a fourth metal layer, wherein the first metal layer of the MEMS acceleration sensor chip and the third metal layer of the chip carrier are bonded together, and the second metal layer and the fourth metal layer are only in contact but not bonded. 2. The low-stress packaging structure according to claim 1 , wherein the third metal layer is composed of two adjacent third metal sub-layers. 3. The low-stress packaging structure according to claim 1 , wherein the first metal layer and the second metal layer are made of titanium/gold, while the third metal layer and the fourth metal layer are made of nickel/gold. 4. The low-stress packaging structure according to claim 1 , wherein the groove has a width of not smaller than 100 μm, and a depth of not smaller than 10 μm. 5. The low-stress packaging structure according to claim 1 , wherein an expansion gap is defined between the MEMS acceleration sensor chip and cavity walls of the chip carrier. 6. The low-stress packaging structure according to claim 5 , wherein the first metal layer of the MEMS acceleration sensor chip and the third metal layer of the chip carrier are bonded together by a gold-tin solder layer. 7. The low-stress packaging structure according to claim 5 , wherein the expansion gap has a width of not smaller than 0.1 mm. 8. The low-stress packaging structure according to claim 1 , wherein bonding pads on the MEMS acceleration sensor chip and bonding pads in the die attach area of the chip carrier are connected to each other via metal leads. 9. The low-stress packaging structure according to claim 1 , further comprising a metal cap configured to seal the die attach area of the chip carrier. 10. A semiconductor package, comprising: a MEMS acceleration sensor chip provided with a first metal layer and a second metal at the bottom of the MEMS acceleration sensor chip and along a first direction, a groove being arranged between the first metal layer and the second metal layer and close to the first metal layer; and a chip carrier provided with a third metal layer and a fourth metal layer on a die attach area of the chip carrier and along the first direction, wherein the third metal layer and the first metal layer are arranged oppositely, the fourth metal layer and the second metal layer are arranged oppositely, the first metal layer and the third metal layer are bonded together, and the second metal layer and the fourth metal layer are only in contact but not bonded. 11. The semiconductor package according to claim 10 , wherein two adjacent first metal sub-layers are arranged at the bottom of the MEMS acceleration sensor chip along a second direction, and two adjacent third metal sub-layers are arranged on the die attach area of the chip carrier along the second direction, the second direction being perpendicular to the first direction. 12. The semiconductor package according to claim 10 , wherein one first metal layer is arranged at the bottom of the MEMS acceleration sensor chip along a second direction, and two adjacent third metal sub-layers are arranged on the die attach area of the chip carrier along the second direction, the second direction being perpendicular to the first direction. 13. The semiconductor package according to claim 10 , wherein the first metal layer and the second metal layer are made of titanium/gold, while the third metal layer and the fourth metal layer are made of nickel/gold. 14. The semiconductor package according to claim 10 , wherein the groove has a width of not smaller than 100 μm, and a depth of not smaller than 10 μm. 15. The semiconductor package according to claim 10 , wherein a gap is defined between a periphery of the MEMS acceleration sensor chip and cavity walls of the chip carrier. 16. The semiconductor package according to claim 15 , wherein the first metal layer and the third metal layer are bonded together by a gold-tin solder layer. 17. The semiconductor package according to claim 15 , wherein the gap has a width of not smaller than 0.1 mm. 18. The semiconductor package according to claim 10 , wherein bonding pads on the MEMS acceleration sensor chip and bonding pads in the die attach area of the chip carrier are connected to each other via metal leads. 19. The semiconductor package according to claim 10 , further comprising a metal cap configured to seal the die attach area of the chip carrier.
between the MEMS die and the substrate · CPC title
for reducing stress inside of the package structure · CPC title
containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS] (B81B7/04 takes precedence) · CPC title
for reducing stress inside of the package structure · CPC title
for acceleration measuring devices · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.