Semiconductor device and method of manufacture

Patent metadata

Field	Value
Publication number	US-11776853-B2
Application number	US-202217646763-A
Country	US
Kind code	B2
Filing date	Jan 3, 2022
Priority date	Apr 28, 2016
Publication date	Oct 3, 2023
Grant date	Oct 3, 2023

Abstract

A semiconductor device and method of manufacture are provided in which a passivation layer is patterned. In embodiments, by-products from the patterning process are removed using the same etching chamber and at the same time as the removal of a photoresist utilized in the patterning process. Such processes may be used during the manufacturing of FinFET devices.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
placing a semiconductor substrate into a first chamber;
prior to removing the semiconductor substrate from the first chamber, etching a passivation layer through a photoresist layer;
prior to removing the semiconductor substrate from the first chamber, performing a liner removal process to expose an external connection through the passivation layer, wherein after the liner removal process reaction by-products are present along sidewalls of the passivation layer, and wherein a first portion of the external connection has a sidewall aligned with a dielectric material, a second portion of the external connection being embedded within the dielectric material; and
prior to removing the semiconductor substrate from the first chamber, removing the photoresist layer and the reaction by-products.

2. The method of claim 1 , wherein the etching the passivation layer comprises:
a chucking step with a first set of parameters;
a main etching step with a second set of parameters different from the first set of parameters; and
an overetching step.

3. The method of claim 2 , wherein the main etching step further comprises:
a first etching step introducing a first etchant; and
a second etching step wherein a flow rate of the first etchant is ended.

4. The method of claim 1 , wherein the etching the passivation layer forms an opening, the opening having a width between about 1 μm and about 10 μm.

5. The method of claim 1 , wherein the removing the photoresist layer and the reaction by-products is performed with oxygen as an only etchant.

6. The method of claim 5 , wherein the removing the photoresist layer and the reaction by-products is performed at a pressure between about 50 mT and about 1000 mT.

7. The method of claim 6 , wherein the oxygen is introduced at a flow rate of between about 500 sccm and about 1800 sccm.

8. A method of manufacturing a semiconductor device, the method comprising:
applying a photoresist to a passivation layer over an external contact over a semiconductor substrate;
removing the photoresist, the removing the photoresist comprising:
a pre-heating removal step with a first set of process conditions;
a stabilization ashing step with a second set of process conditions different from the first set of process conditions; and
a stripping step with a third set of process conditions different from the first set of process conditions and different from the second set of process conditions, the stripping step removing both the photoresist as well as reaction by-products from a previous etching process.

9. The method of claim 8 , wherein the passivation layer is a composite layer.

10. The method of claim 9 , wherein the composite layer comprises:
a first layer with a first material and a first thickness between about 2 KÅ and about 4 KÅ; and
a second layer with a second material and a second thickness between about 2 KÅ and about 6 KÅ, the second material being different from the first material.

11. The method of claim 8 , wherein the first set of process conditions comprises:
a pressure between about 500 mT and about 6000 mT;
a temperature between about 50° C. and about 200° C.; and
an etchant flow rate between about 100 sccm and about 9000 sccm.

12. The method of claim 8 , wherein the second set of process conditions comprises a second pressure between about 50 mT and about 1500 mT.

13. The method of claim 12 , wherein the second set of process conditions further comprises a second flow rate between about 500 sccm and about 5400 sccm.

14. The method of claim 8 , further comprising a liner removal step.

15. The method of claim 14 , wherein the liner removal step comprises:
a ramping step; and
a removal step, wherein the removal step is performed with a higher pressure than the ramping step.

16. A method of manufacturing a semiconductor device, the method comprising:
placing a semiconductor substrate into a first chamber;
etching a passivation layer through a photoresist layer;
performing a liner removal process to expose an external connection through the passivation layer, wherein after the liner removal process reaction by-products are present along sidewalls of the passivation layer; and
removing the photoresist and the reaction by-products, wherein the etching, the performing, and the removing are each performed in a first chamber, and wherein the removing further comprises:
performing a heating step with a first set of process conditions;
modifying the first set of process conditions to a second set of process conditions in a stabilization step; and
modifying the second set of process conditions to a third set of process conditions in a stripping step, the stripping step removing both the photoresist as well as the reaction by-products from a previous etching process.

17. The method of claim 16 , wherein the first set of process conditions comprises:
a pressure between about 500 mT and about 6000 mT;
a temperature between about 50° C. and about 200° C.; and
an etchant flow rate between about 100 sccm and about 9000 sccm.

18. The method of claim 17 , wherein the second set of process conditions comprises a second pressure between about 50 mT and about 1500 mT.

19. The method of claim 18 , wherein the second set of process conditions further comprises a second flow rate between about 500 sccm and about 5400 sccm.

20. The method of claim 16 , wherein within the stripping step oxygen is an only etchant utilized.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Hung-Hao
• Chang Che-Cheng
• Tseng Horng-Huei
• Chen Wen-Tung
• Liu Yu-Cheng

Classifications

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W72/01938

  in gaseous form, e.g. by CVD or PVD · CPC title