Histogram operation

Patent metadata

Field	Value
Publication number	US-11775302-B2
Application number	US-202117509218-A
Country	US
Kind code	B2
Filing date	Oct 25, 2021
Priority date	May 27, 2019
Publication date	Oct 3, 2023
Grant date	Oct 3, 2023

Abstract

A digital data processor includes an instruction memory storing instructions each specifying a data processing operation and at least one data operand field, an instruction decoder coupled to the instruction memory for sequentially recalling instructions from the instruction memory and determining the data processing operation and the at least one data operand, and at least one operational unit coupled to a data register file and to an instruction decoder to perform a data processing operation upon at least one operand corresponding to an instruction decoded by the instruction decoder and storing results of the data processing operation. The operational unit is configured to increment histogram values in response to a histogram instruction by incrementing a bin entry at a specified location in a specified number of at least one histogram.

First claim

What is claimed is:

1. A processor comprising:
a cache configured to store a set of tables; and
a set of registers that includes a first register configured to store a set of indices each corresponding to a respective value stored in a respective table of the set of tables, wherein the processor is configured to:
receive an instruction that specifies the first register and the set of tables; and
based on the instruction, for each index in the set of indices, increment the respective value stored in the respective table of the set of tables.

2. The processor of claim 1 , wherein the set of indices includes a first index corresponding to a first value stored in a first table of the set of tables and a second index corresponding to a second value stored in a second table of the set of tables that is different from the first table.

3. The processor of claim 1 , wherein:
the set of tables includes a plurality of tables;
the set of indices includes a plurality of indices; and
the processor is configured to, based on the instruction, increment a plurality of values stored in the plurality of tables associated with the plurality of indices.

4. The processor of claim 1 , wherein the cache is a level one (L1) data cache.

5. The processor of claim 1 , wherein the processor is configured to, based on the instruction, for each index in the set of indices, increment the respective value stored in the respective table of the set of tables by one.

6. The processor of claim 1 , wherein:
the set of registers includes a second register configured to store a set of weighting values associated with the set of indices;
the instruction specifies the second register; and
the processor is configured to, based on the instruction, for each index in the set of indices, increment the respective value stored in the respective table of the set of tables by a respective weighting value of the set of weighting values.

7. The processor of claim 1 , wherein:
the set of registers includes a second register configured to store a base address for the set of tables; and
the instruction specifies the set of tables by specifying the second register.

8. The processor of claim 1 , wherein:
the set of registers includes a second register configured to store a configuration for the set of tables; and
the instruction specifies the second register.

9. The processor of claim 8 wherein the configuration stored in the second register specifies the number of tables in the set of tables.

10. The processor of claim 8 , wherein the configuration stored in the second register specifies at least one parameter from a group consisting of: a promotion mode for values of the set of tables, a table size for the set of tables, whether to saturate the values of the set of tables, whether the values of the set of tables are signed, and an element size for the set of tables.

11. The processor of claim 1 further comprising:
an instruction memory configured to store the instruction;
an instruction decoder coupled to the instruction memory; and
at least one operational unit coupled to the instruction decoder, the cache and the set of registers, wherein the instruction decoder is configured to cause the at least one operational unit to, based on the instruction, for each index in the set of indices, increment the respective value stored in the respective table of the set of tables.

12. A processor comprising:
a cache configured to store a set of tables; and
a set of registers that includes:
a first register configured to store a set of indices each corresponding to a respective value stored in a respective table of the set of tables; and
a second register configured to store a set of weighting values associated with the set of indices;

wherein the processor is configured to:
receive an instruction that specifies the first register, the second register, and the set of tables; and
based on the instruction, for each index in the set of indices, add a respective weighting value of the set of weighting values to the respective value stored in the respective table of the set of tables.

13. The processor of claim 12 , wherein:
the set of tables includes a plurality of tables;
the set of indices includes a plurality of indices;
the set of weighting values includes a plurality of weighting values; and
the processor is configured to, based on the instruction, add the plurality of weighting values to a plurality of values stored in the plurality of tables associated with the plurality of indices.

14. The processor of claim 12 , wherein the cache is a level one (L1) data cache.

15. A method comprising:
storing a set of values arranged in a set of tables in a cache memory of a processor;
storing a set of indices each corresponding to a respective value of the set of values;
receiving an instruction that specifies the set of tables and the set of indices; and
based on the instruction, for each index in the set of indices, incrementing the respective value of the set of values.

16. The method of claim 15 , wherein the set of indices includes a first index corresponding to a first value of a first table of the set of tables and a second index corresponding to a second value of a second table of the set of tables that is different from the first table.

17. The method of claim 15 , wherein the cache memory is a level one (L1) data cache memory.

18. The method of claim 15 , wherein the incrementing includes, for each index in the set of indices, incrementing the respective value of the set of values by one.

19. The method of claim 15 further comprising storing a set of weighting values associated with the set of indices, wherein the incrementing includes, for each index in the set of indices, incrementing the respective value of the set of values by a respective weighting value of the set of weighting values.

20. The method of claim 19 , wherein at least one weighting value of the set of weighting values is negative.

Assignees

• Texas Instruments Inc

Inventors

• Bhoria Naveen
• Bui Duc
• Venkatasubramanian Rama
• Samudrala Dheera Balasubramanian
• Davis Alan

Classifications

• G06F9/3001 Primary

  Arithmetic instructions · CPC title

• G06F9/30145 Primary

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/30007

  to perform operations on data operands · CPC title

• G06F9/30032

  Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title