Maintaining synchronisation between memory writing and reading blocks using an internal buffer and a control channel

Patent metadata

Field	Value
Publication number	US-11775206-B2
Application number	US-202117336701-A
Country	US
Kind code	B2
Filing date	Jun 2, 2021
Priority date	Jun 2, 2020
Publication date	Oct 3, 2023
Grant date	Oct 3, 2023

Abstract

A hardware unit for manipulating data stored in a memory comprises an internal buffer, a memory reading block, configured to read the data from the memory and write the data to the internal buffer. a memory writing block, configured to read the data from the internal buffer and write the data to the memory. The hardware unit optionally also comprises a control channel between the memory reading block and the memory writing block, wherein the memory reading block and the memory writing block are configured to communicate via the control channel to maintain synchronisation between them when writing the data to the internal buffer and reading the data from the internal buffer, respectively. The hardware unit may be configured to apply one or more transformations to multidimensional data in the memory. The hardware unit may be configured to traverse the multidimensional array using a plurality of nested loops.

First claim

What is claimed is:

1. A hardware unit for manipulating data stored in a memory, the hardware unit comprising:
an internal buffer;
a memory reading block, configured to read the data from the memory and write the data to the internal buffer;
a memory writing block, configured to read the data from the internal buffer and write the data to the memory; and
a control channel between the memory reading block and the memory writing block, wherein the memory reading block and the memory writing block are configured to communicate via the control channel to maintain synchronisation between them when writing the data to the internal buffer and reading the data from the internal buffer, respectively;
wherein the memory reading block is configured to read the data from the memory in discrete bursts and/or the memory writing block is configured to write the data to the memory in discrete bursts, the discrete bursts having a predetermined first size,
wherein the memory reading block is configured to write the data to the internal buffer in discrete units and/or the memory writing block is configured to read the data from the internal buffer in discrete units, the discrete units having a second size,
wherein the second size is different from the first size,
wherein the data comprises a multidimensional array comprising a plurality of data elements, wherein at least one of the memory reading block and the memory writing block is configured to traverse the multidimensional array using a plurality of nested loops, each loop having associated with it a corresponding stride between data elements of the multidimensional array, and
wherein, when reading or writing a desired segment of the multidimensional array, said at least one block is configured to select the number of iterations in at least one loop, based on a relationship between the size of the desired segment and the first size.

2. The hardware unit of claim 1 , wherein the data comprises a multidimensional array comprising a plurality of data elements, wherein at least one of the memory reading block and the memory writing block is configured to traverse the multidimensional array using a plurality of nested loops, each loop having associated with it a corresponding stride between data elements of the multidimensional array.

3. The hardware unit of claim 2 , wherein at least one loop of the plurality of nested loops is configured to iterate a different number of times depending on at least one of:
(a) a loop index of at least one other loop of the plurality of nested loops; and
(b) a software configurable flag.

4. The hardware unit of claim 2 , wherein each loop of the plurality of loops is configured to perform a variable number of iterations, the variable number being selected at runtime from a group comprising:
a first number of iterations to be performed when one or more outer loops of the plurality of nested loops are not in their end iteration; and
a second number of iterations to be performed when the one or more outer loops of the plurality of nested loops are in their end iteration.

5. The hardware unit of claim 1 , wherein said at least one block is configured to:
determine, based on said relationship, that a discrete burst to be read or written contains extra data, which is additional to the desired segment and which is scheduled to be read or written in a later iteration of at least one of the plurality of loops; and
in response, to operate on the extra data in the current iteration according to an operation scheduled for said later iteration.

6. The hardware unit of claim 1 , wherein the data comprises a multidimensional array comprising a plurality of data elements,
wherein the multidimensional array is stored in the memory in a storage format having storage units of a predetermined third size, wherein one or more dimensions of the multidimensional array are not an integer multiple of the third size.

7. The hardware unit of claim 6 , wherein at least one of the memory reading block and the memory writing block is configured to traverse the multidimensional array using a plurality of nested loops, each loop having associated with it a corresponding stride between data elements of the multidimensional array,
wherein said at least one block is configured to select, for at least one loop of the plurality of nested loops, a different number of iterations when one or more outer loops are in their end iteration, as compared with the number of iterations of said at least one loop when the one or more outer loops are not in their end iteration.

8. The hardware unit of claim 1 , wherein each of the memory reading block and the memory writing block has a respective synchronisation counter,
the blocks being configured to communicate their synchronisation counters with each other via the control channel,
wherein the hardware unit is configured to maintain synchronisation between the blocks by comparing the synchronisation counters.

9. The hardware unit of claim 8 , wherein the data comprises a multidimensional array comprising a plurality of data elements, wherein each of the memory reading block and the memory writing block is configured to traverse the multidimensional array using a respective plurality of nested loops, each loop having associated with it a corresponding stride between data elements of the multidimensional array,
wherein the synchronisation counter of the memory reading block is associated with a first loop of its plurality of loops and the synchronisation counter of the memory writing block is associated with a second loop of its plurality of loops.

10. A hardware-implemented method of manipulating data stored in a memory, the data comprising a multidimensional array comprising a plurality of data elements, the method comprising:
(i) reading the data from the memory and writing the data to the internal buffer; and
(ii) reading the data from the internal buffer and writing the data to the memory, wherein at least one of the steps (i) and (ii) is performed using a plurality of nested loops, each loop having associated with it a corresponding stride between data elements of the multidimensional array,
wherein at least one loop of the plurality of nested loops is configured to iterate a different number of times depending on a loop index of at least one other loop of the plurality of nested loops;
wherein the data is read from the memory in discrete bursts, and/or the data is written to the memory in discrete bursts, the discrete bursts having a predetermined first size;
wherein the data is written to the internal buffer in discrete units, and/or the data is read from the internal buffer in discrete units, the discrete units having a second size;
wherein the second size is different from the first size, and
wherein, when reading or writing a desired segment of the multidimensional array from or to the memory, respectively, selecting the number of iterations in at least one loop, based on a relationship between the size of the desired segment and the first size.

11. The method of claim 10 , wherein at least one loop of the plurality of nested loops is further configured to iterate a different number of times depending on a software configurable flag.

12. The method of claim 10 , wherein each loop of the plurality of loops is configured to perform a variable number of iterations, the variable number being selected at runtime from a group comprising:
a first number of iterations to be performed when one or more outer loops of the plurality of nested loops are in their first iteration;
a second number of iterations to be performed when the one or more outer loops of the plurality of nested l

Assignees

• Imagination Tech Ltd

Inventors

• Vines Alan
• Spain Stephen
• Escobar Fernando

Classifications

• G06F3/0656 Primary

  Data buffering arrangements · CPC title

• G06F3/061

  Improving I/O performance · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F13/1673 Primary

  using buffers · CPC title

• G06F3/064

  Management of blocks · CPC title