Synchronizing systems on a chip using a shared clock

Patent metadata

Field	Value
Publication number	US-11775005-B2
Application number	US-202117495311-A
Country	US
Kind code	B2
Filing date	Oct 6, 2021
Priority date	Oct 6, 2021
Publication date	Oct 3, 2023
Grant date	Oct 3, 2023

Abstract

An electronic eyewear device includes first and second systems on a chip (SoCs) having independent time bases that are synchronized by generating a common clock signal from a clock generator of the first SoC and simultaneously applying the common clock signal to a first counter of the first SoC and a second counter of the second SoC whereby the first counter and the second counter count clock edges of the common clock. The clock counts are shared through an interface between the first SoC and the second SoC and compared to each other. When the clock counts are different, a clock count of the first counter or the second counter is adjusted to cause the clock counts to match each other. The adjusted clock count is synchronized to the respective clocks of the first and second SoCs, thus synchronizing the first and second SoCs to each other.

First claim

What is claimed is:

1. A method of synchronizing first and second systems-on-chip (SoCs) of an electronic eyewear device, the first and second SoCs having independent time bases, the method comprising:
a first clock generator of the first SoC generating a common clock;
resetting a first counter of the first SoC and a second counter of the second SoC, wherein the first counter and the second counter have independent time bases;
simultaneously applying the common clock to the first counter and the second counter whereby the first counter and the second counter count clock edges of the common clock;
sharing timestamps of the first counter and the second counter;
comparing the timestamps of the first counter and the second counter;
when the timestamps are different, adjusting a clock count of at least one of the first counter or the second counter to cause the clock counts of the first counter and the second counter to match each other; and
after the adjusting, using the clock count of the first counter to synchronize to a clock output by the first clock generator and the clock count of the second counter to synchronize to a clock output by a second clock generator of the second SoC so as to synchronize the clocks output by the first clock generator and the second clock generator to each other.

2. The method of claim 1 , wherein the first clock generator generating the common clock comprises dividing a clock signal from a crystal of the first clock generator to generate the common clock.

3. The method of claim 1 , wherein resetting the first counter and the second counter comprises providing a reset pulse to the first counter and the second counter.

4. The method of claim 3 , wherein resetting the first counter and the second counter comprises applying the reset pulse to the first counter and the second counter when at least one of the first SoC or the second SoC is rebooted or changes power state.

5. The method of claim 1 , wherein resetting the first counter and the second counter comprises applying an out of band interrupt or manual reset pulse to the first counter and the second counter.

6. The method of claim 1 , wherein sharing the timestamps of the first counter and the second counter comprises providing a timestamp of a clock count of the first counter over an inter-SoC interface to the second SoC.

7. The method of claim 1 , wherein adjusting a clock count of at least one of the first counter or the second counter to cause the clock counts of the first counter and the second counter to match each other comprises setting the clock counts of the first counter and the second counter to a same count.

8. The method of claim 1 , wherein sharing timestamps of the first counter and the second counter, comparing the timestamps of the first counter and the second counter, adjusting the clock count of at least one of the first counter or the second counter to cause the clock counts of the first counter and the second counter to match each other when the clock counts are different, and after the adjusting, using the clock count of the first counter to synchronize to the clock output by the first clock generator and the clock count of the second counter to synchronize to the clock output by a second clock generator of the second SoC are repeated periodically to adjust timing between the first SoC and the second SoC to adjust for drift over time between clock signals generated by the first clock generator and the second clock generator.

9. The method of claim 1 , wherein at least one of the first counter or the second counter comprises a hardware counter.

10. An electronic eyewear device comprising:
a first system-on-chip (SoC) comprising a first counter and a first clock generator that generates at least one clock signal for the first SoC and a common clock signal derived from the at least one clock signal;
a second SoC comprising a second counter and a second clock generator that generates at least one clock signal for the second SoC, the first clock generator and the second clock generator having independent time bases and the common clock signal being simultaneously applied to the first counter and the second counter upon reset of the first counter and the second counter whereby the first counter and the second counter count clock edges of the common clock;
an interface through which timestamps of the first counter and the second counter are shared between the first SoC and the second SoC; and
a computer readable medium comprising instructions stored thereon that are executable by at least one of the first SoC or the second SoC to cause the at least one of the first SoC or the second SoC to perform operations for synchronizing the first SoC and the second SoC, the operations including:
comparing the timestamps of the first counter and the second counter;
when the timestamps are different, adjusting a clock count of at least one of the clock count of the first counter or the clock count of the second counter to cause the clock count of the first counter and the clock count of the second counter to match each other; and
after the adjusting, using the clock count of the first counter to synchronize to a clock of the first clock generator and the clock count of the second counter to synchronize to a clock of the second clock generator so as to synchronize the clocks of the first clock generator and the second clock generator to each other.

11. The electronic eyewear device of claim 10 , wherein the first clock generator comprises a divider and a crystal, the divider generating the common clock signal by dividing a clock signal from the crystal.

12. The electronic eyewear device of claim 10 , wherein at least one of the first SoC or the second SoC provides a reset pulse to the first counter and the second counter to reset the first counter and the second counter.

13. The electronic eyewear device of claim 12 , wherein at least one of the first SoC or the second SoC applies the reset pulse to the first counter and the second counter when the at least one of the first SoC or the second SoC is rebooted or changes power state.

14. The electronic eyewear device of claim 10 , further comprising a reset line connecting the first counter and the second counter for applying an out of band interrupt or manual reset pulse to the first counter and the second counter.

15. The electronic eyewear device of claim 10 , wherein the interface comprises a Peripheral Component Interconnect Express (PCIe) interconnect.

16. The electronic eyewear device of claim 10 , wherein the instructions for adjusting the clock count of at least one of the clock count of the first counter or the clock count of the second counter to cause the clock count of the first counter and the clock count of the second counter to match each other comprises instructions that when executed cause the clock counts of the first counter and the second counter to be set to a same count.

17. The electronic eyewear device of claim 10 , wherein the instructions for comparing the timestamps of the first counter and the second counter, adjusting the clock count of at least one of the clock count of the first counter or the clock count of the second counter to cause the clock count of the first counter and the clock count of the second counter to match each other, and after the adjusting, using the clock count of the first counter to synchronize to the clock of the first clock generator and the clock count of the second counter to synchronize to the clock of the second clock generator so as to synchronize the clocks of the first clock generator an

Assignees

• Ahn Samuel
• Heger Jason
• Ryuma Dmitry
• Snap Inc

Inventors

• Ahn Samuel
• Heger Jason
• Ryuma Dmitry

Classifications

• G06F2213/0026

  PCI express · CPC title

• G06F3/011

  Arrangements for interaction with the human body, e.g. for user immersion in virtual reality (blind teaching G09B21/00) · CPC title

• G06F15/17325

  Synchronisation; Hardware support therefor (intertask synchronisation G06F9/52) · CPC title

• G06F13/4221

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title

• G06F1/14

  Time supervision arrangements, e.g. real time clock · CPC title