Redundant clock switch

Patent metadata

Field	Value
Publication number	US-11775002-B2
Application number	US-202117386043-A
Country	US
Kind code	B2
Filing date	Jul 27, 2021
Priority date	Jul 27, 2021
Publication date	Oct 3, 2023
Grant date	Oct 3, 2023

Abstract

A first oscillator signal and a second oscillator signal are transmitted to a processing unit. The first oscillator signal has a finite frequency or phase offset relative to the second oscillator signal. A first clock signal that is derived from the first oscillator signal is selected as a primary clock to clock the processing unit. A second clock signal derived from the second oscillator signal is aligned to the first clock signal. If a fault is detected on the first clock signal, the second clock signal is selected as the primary clock to clock the processing unit. Upon being selected as the primary clock, the phase of the second is stretched by one fixed phase for one clock cycle.

First claim

What is claimed is:

1. A redundant clock switch (RCS) clocking method comprising:
deriving, with the RCS, a first clock signal from a first oscillator signal received by the RCS from a first oscillator;
deriving, with the RCS, a second clock signal from a second oscillator signal received by the RCS from a second oscillator, the second oscillator signal comprising a frequency or phase offset relative to the first oscillator signal;
selecting, with the RCS, the first clock signal as a reference clock output from the RCS; and
aligning, with the RCS, the second clock signal to the first clock signal by determining widths of increment pulses and determining widths of decrement pulses, comparing the widths of increment pulses with the widths of decrement pulses, and based upon the comparison, rotating a phase of the second clock signal to align with a phase of the first clock signal.

2. The RCS clocking method of claim 1 , further comprising:
detecting, with the RCS, a fault to the first clock signal;
upon detecting the fault to the first clock signal, stretching, with the RCS, the second clock signal by a lagging phase; and
upon detecting the fault to the first clock signal, selecting, with the RCS, the second clock signal as the reference clock output from the RCS.

3. The RCS clocking method of claim 2 , wherein the reference clock output comprises a stretched period for one clock cycle that includes switchover of the second clock being selected as the reference clock output.

4. The RCS clocking method of claim 1 , wherein rotating the phase of the second clock signal to align with the phase of the first clock signal comprises:
aligning rising edges of the second clock signal to rising edges of the first clock signal.

5. The RCS clocking method of claim 1 , wherein deriving the first clock signal from the first oscillator signal comprises:
creating N copies of the first oscillator signal;
simultaneous shifting the N copies of the first oscillator signal by a fixed number of degrees to create N copies of the first oscillator signal each separated by a fixed phase;
identifying a first delayed clock that lags the first oscillator signal by one fixed phase; and
selecting the first delayed clock as the first clock signal.

6. The RCS clocking method of claim 2 , wherein deriving the second clock signal from the first oscillator signal comprises:
creating N copies of the second oscillator signal;
simultaneous shifting the N copies of the second oscillator signal by a fixed number of degrees to create N copies of the second oscillator signal each separated by a fixed phase;
identifying a second delayed clock that lags the second oscillator signal by one fixed phase; and
selecting the second delayed clock as the second clock signal.

7. The RCS clocking method of claim 6 , wherein upon detecting the fault to the first clock signal, stretching the second clock signal by the lagging phase comprises:
upon detecting the fault to the first clock signal, advancing the second clock signal by one fixed phase.

8. An electronic device comprising:
a first oscillator that generates a first oscillator signal;
a second oscillator that generates a second oscillator signal, the second oscillator signal comprising a frequency or phase offset relative to the first oscillator signal;
a redundant clock switch comprising a primary side communicatively connected to the first oscillator and a redundant side communicatively connected to the second oscillator;
a primary phase rotator within the primary side that derives a primary clock signal from the first oscillator signal;
a multiplexer that selects the primary clock signal as an output reference clock that clocks a processing unit;
a redundant phase rotator within the redundant side that derives a redundant clock signal from the second oscillator signal and aligns the redundant clock signal to the primary clock signal; and
a phase frequency detector that receives the primary clock and the redundant clock and outputs increment pulses and decrement pulses therefrom, wherein widths of the increment pulses are proportional to timing differences between leading rising edges of the primary clock and leading trailing edges of the redundant clock and wherein widths of the decrement pulses are proportional to timing differences between leading rising edges of the redundant clock and leading trailing edges of the primary clock.

9. The electronic device of claim 8 , further comprising:
a primary error detector within the primary side that detects faults of the primary clock signal and sends a primary clock error signal to the redundant phase rotator.

10. The electronic device of claim 9 , wherein the redundant phase rotator stretches the redundant clock signal by a lagging phase upon receipt of the primary clock error signal.

11. The electronic device of claim 10 , wherein the multiplexer selects the second clock signal as the reference clock upon the redundant phase rotator receiving the primary clock error signal.

12. The electronic device of claim 11 , wherein the reference clock comprises a stretched period for one clock cycle that includes switchover of the second clock being selected as the reference clock.

13. The electronic device of claim 8 , wherein the redundant phase rotator compares widths of the increment pulses to widths of the decrement pulses and rotates a phase of the redundant clock signal to align rising edges of the redundant clock signal to rising edges of the primary clock signal.

14. The electronic device of claim 13 , wherein the redundant rotator shifts N copies of the second oscillator signal by a fixed number of degrees to create N copies of the second oscillator signal each separated by a fixed phase, identifies a delayed clock that lags the second oscillator signal by one fixed phase, and selects the second delayed clock as the redundant clock signal.

15. The electronic device of claim 14 , wherein the redundant phase rotator advances the second clock signal by one fixed phase in response to the receipt of the primary clock error signal.

16. A method comprising:
transmitting a first oscillator signal and second oscillator signal to a processing unit, the first oscillator signal comprising a finite frequency or phase offset relative to the second oscillator signal;
powering the processing unit;
selecting a first clock signal derived from the first oscillator signal as a primary clock to clock the processing unit;
aligning rising edges of a second clock signal derived from the second oscillator signal to rising edges of the first clock signal by determining widths of increment pulses and determining widths of decrement pulses, comparing the widths of increment pulses with the widths of decrement pulses, and based upon the comparison, rotating a phase of the second clock signal to align with a phase of the first clock signal;
checking for a fault on the first clock signal; and
if a fault is detected on the first clock signal, selecting the second clock signal as the primary clock to clock the processing unit.

17. The method of claim 16 , further comprising:
if a fault is detected on the first clock signal, stretching the second clock signal by a lagging phase.

18. The method of claim 17 , wherein the primary clock comprises a stretched period for one clock cycle that includes switchover of the second clock signal being selected as the primary clock.

19. The method of claim 16 , wherein rotating the phase of the second clock signal to align with the phase of the

Assignees

• IBM

Inventors

• Paschal Matthew James
• Dreps Daniel M
• Wiedemeier Glen A
• Rudolph Bruce George
• Strom James

Classifications

• G06F1/08 Primary

  Clock generators with changeable or programmable clock frequency · CPC title

• G06F1/12

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• G06F1/10

  Distribution of clock signals {, e.g. skew} · CPC title