Clock generation circuit and clock signal generation method

Patent metadata

Field	Value
Publication number	US-10778234-B2
Application number	US-201816204790-A
Country	US
Kind code	B2
Filing date	Nov 29, 2018
Priority date	May 31, 2016
Publication date	Sep 15, 2020
Grant date	Sep 15, 2020

Abstract

A clock generation circuit and a clock signal generation method are disclosed. In the method, a direct current bias circuit in a first clock source superimposes a first direct current voltage on a first clock signal output by a first oscillation circuit, to generate a second clock signal; and a logical operation is performed on the second clock signal and a third clock signal that is generated by a second clock source, to generate a fourth clock signal. The fourth clock signal is used as a signal output by a clock generation circuit. In the method, when the first oscillation circuit cannot normally work, the clock generation circuit can still output a correct clock signal. This avoids clock signal interruption when switching is performed from the first clock source to the second clock source.

First claim

What is claimed is:

1. A clock generation circuit, comprising a first clock source, a second clock source, and a logic gate circuit, wherein the first clock source is coupled to the logic gate circuit and the second clock source is coupled to the logic gate circuit, the first clock source comprises a first oscillation circuit and a first direct current bias circuit, the first oscillation circuit is coupled to the first direct current bias circuit, and the first direct current bias circuit is coupled to the logic gate circuit, wherein
the first oscillation circuit is configured to generate a first clock signal;
the first direct current bias circuit is configured to: remove a direct current component from the first clock signal, and superimpose a first direct current voltage on the first clock signal obtained after the direct current component is removed, to generate a second clock signal, wherein a voltage value of the first direct current voltage is greater than a high-level decision threshold of the logic gate circuit, and the voltage value of the first direct current voltage is less than a difference between a low-level decision threshold of the logic gate circuit and a low-level voltage value of the first clock signal;
the second clock source is configured to generate a third clock signal, wherein an absolute value of a difference between a frequency of the third clock signal and a frequency of the second clock signal is less than a first preset value; and
the logic gate circuit is configured to: receive the second clock signal and the third clock signal, and perform an AND logical operation on the second clock signal and the third clock signal to generate a fourth clock signal.

2. The clock generation circuit according to claim 1 , wherein the second clock source comprises a second oscillation circuit and a second direct current bias circuit, the second oscillation circuit is coupled to the second direct current bias circuit, and the second direct current bias circuit is coupled to the logic gate circuit, wherein
the second oscillation circuit is configured to generate a fifth clock signal; and
the second direct current bias circuit is configured to: remove a direct current component from the fifth clock signal, and superimpose a second direct current voltage on the fifth clock signal obtained after the direct current component is removed, to generate the third clock signal, wherein a voltage value of the second direct current voltage is greater than the high-level decision threshold of the logic gate circuit, and the voltage value of the second direct current voltage is less than a difference between the low-level decision threshold of the logic gate circuit and a low-level voltage value of the fifth clock signal.

3. The clock generation circuit according to claim 1 , wherein the second clock source is a controlled clock source, and the clock generation circuit further comprises a control circuit, wherein
the control circuit is configured to: generate a control signal according to a phase difference and/or a frequency difference between the second clock signal and the third clock signal, and send the control signal to the second clock source; and
the control signal is used to control the frequency of the third clock signal, so that the absolute value of the difference between the frequency of the third clock signal and the frequency of the second clock signal is less than the first preset value.

4. The clock generation circuit according to claim 1 , wherein a first delay circuit is further coupled between the first oscillation circuit and the logic gate circuit; and
the first delay circuit is configured to delay the second clock signal, so that a difference between a time at which the first direct current bias circuit outputs the second clock signal and a time at which the logic gate circuit receives the second clock signal is first duration; or
the first delay circuit is configured to delay the first clock signal, so that a difference between a time at which the first oscillation circuit outputs the first clock signal and a time at which the first direct current bias circuit receives the first clock signal is second duration.

5. The clock generation circuit according to claim 1 , wherein a second delay circuit is further coupled between the second clock source and the logic gate circuit; and
the second delay circuit is configured to delay the third clock signal, so that a difference between a time at which the second clock source outputs the third clock signal and a time at which the logic gate circuit receives the third clock signal is first duration.

6. The clock generation circuit according to claim 2 , wherein a second delay circuit is further coupled between the second oscillation circuit and the logic gate circuit; and
the second delay circuit is configured to delay the third clock signal, so that a difference between a time at which the second direct current bias circuit outputs the third clock signal and a time at which the logic gate circuit receives the third clock signal is first duration; or
the second delay circuit is configured to delay the fifth clock signal, so that a difference between a time at which the second oscillation circuit outputs the fifth clock signal and a time at which the second direct current bias circuit receives the fifth clock signal is second duration.

7. The clock generation circuit according to claim 1 , wherein a time at which the logic gate circuit receives a rising edge of the second clock signal is earlier than a time at which the logic gate circuit receives a rising edge of the third clock signal, and a difference between the time at which the logic gate circuit receives the rising edge of the second clock signal and the time at which the logic gate circuit receives the rising edge of the third clock signal is less than high-level duration of the second clock signal; or
a time at which the logic gate circuit receives a rising edge of the second clock signal is later than a time at which the logic gate circuit receives a rising edge of the third clock signal, and a difference between the time at which the logic gate circuit receives the rising edge of the third clock signal and the time at which the logic gate circuit receives the rising edge of the second clock signal is less than high-level duration of the third clock signal.

8. A clock signal generation method, wherein the method is applied to a clock generation circuit, the clock generation circuit comprises a first clock source, a second clock source, and a logic gate circuit, and the first clock source comprises a first oscillation circuit and a first direct current bias circuit; and the method comprises:
generating, by the first oscillation circuit, a first clock signal;
sending, by the first oscillation circuit, the first clock signal to the first direct current bias circuit;
removing, by the first direct current bias circuit, a direct current component from the first clock signal, and superimposing a first direct current voltage on the first clock signal obtained after the direct current component is removed, to generate a second clock signal, wherein a voltage value of the first direct current voltage is greater than a high-level decision threshold of the logic gate circuit, and the voltage value of the first direct current voltage is less than a difference between a low-level decision threshold of the logic gate circuit and a low-level voltage value of the first clock signal;
generating, by the second clock source, a third clock signal, wherein a difference between frequencies of the third clock signal and the second clock signal is less than a first preset value; and
receiving, by the logic gate circuit, the second clock signal and the thi

Assignees

• Huawei Tech Co Ltd

Inventors

• Li Hua
• Gao Yan
• Ma Sheng

Classifications

• G06F11/1604 Primary

  where the fault affects the clock signals of a processing unit and the redundancy is at or within the level of clock signal generation hardware · CPC title

• H03L7/08

  Details of the phase-locked loop · CPC title

• H03L7/099 Primary

  concerning mainly the controlled oscillator of the loop · CPC title