Semiconductor structure and method for forming the same

Patent metadata

Field	Value
Publication number	US-11770977-B2
Application number	US-202017081742-A
Country	US
Kind code	B2
Filing date	Oct 27, 2020
Priority date	Oct 27, 2020
Publication date	Sep 26, 2023
Grant date	Sep 26, 2023

Abstract

A method for fabricating magnetic tunnel junction (MTJ) pillars is provided. The method includes following operations. A MTJ stack of layers including a first magnetic layer, a tunnel barrier layer overlying the first magnetic layer, and a second magnetic layer overlying the tunnel barrier layer is provided. A first patterning step is carried out by using a reactive ion etching. In the first patterning step, the second magnetic layer and the tunnel barrier layer are etched to form one or more pillar structures and a protection layer is formed and covers sidewalk of the pillar structures.

First claim

What is claimed is:

1. A method for fabricating magnetic tunnel junction (MTJ) pillars, the method comprising:
providing a magnetic tunneling junction (MTJ) stack of layers, wherein the MTJ stack of layers comprising a first magnetic layer, a tunnel barrier layer overlying the first magnetic layer, and a second magnetic layer overlying the tunnel barrier layer;
carrying out a first patterning step by using a reactive ion etching, wherein the second magnetic layer and the tunnel barrier layer are etched to form one or more pillar structures and a protection layer is formed and covers sidewalls of the pillar structures, wherein the first patterning step comprises using a first process gas for etching and then using a second process gas for forming the protection layer, and
carrying out a second patterning step by using an ion beam etching, wherein the first magnetic layer is etched such that the pillar structures formed in the first patterning step extend downwardly and include the etched first magnetic layer.

2. The method of claim 1 , wherein the first process gas has a relatively high ratio of fluorine (F) to carbon (C) than the second process gas.

3. The method of claim 1 , wherein the first process gas includes one or more of the following chemical substances: CH 4 , CH 3 F 2 , CHF 3 and CF 4 .

4. The method of claim 3 , wherein the first process gas used in the first patterning step further comprises O 2 .

5. The method of claim 3 , wherein the first process gas used in the first patterning step further comprises one or more of the following chemical substances:
Si x cl y , Si x F y , Si x I y , Cl 2 , Br 2 and an inert gas.

6. The method of claim 1 , wherein the second process gas includes one or more of the following chemical substances: CH 4 , CH 3 F, CH 2 F 2 , CHF 3 and CF 4 .

7. The method of claim 6 , wherein the second process gas used in the first patterning step further comprises O 2 .

8. The method of claim 6 , wherein the second process gas used in the first patterning step further comprises an inert gas.

9. The method of claim 1 , wherein the protection layer has polymer-rich chemistry.

10. The method of claim 1 , wherein the stack of MT layers is provided over a bottom electrode and the bottom electrode is etched together with the first magnetic layer in the second patterning step.

11. The method of claim 1 , wherein a top electrode layer is provided over the second magnetic layer and the top electrode is etched together with the second magnetic layer and the tunnel barrier layer in the first patterning step.

12. The method of claim 1 , wherein the protection layer comprises fluorine (F).

13. A method for fabricating a semiconductor structure, the method comprising:
providing a magnetic tunneling junction (MTJ) stack of layers, wherein the MTJ stack of layers comprising a first magnetic layer, a tunnel barrier layer overlying the first magnetic layer, and a second magnetic layer overlying the tunnel barrier layer;
carrying out a chemical treatment using a process gas containing fluorocarbon to etch the tunnel barrier layer,
forming a protection layer covering sidewalls of the tunnel barrier layer, wherein the protection layer comprises carbon (C), hydrogen (H), and oxygen (O),
patterning the first magnetic layer to create conductive particles,
depositing the conductive particles on the protection layer, and
forming a cap dielectric layer over the conductive particles.

14. The method of claim 13 , wherein carrying out a chemical treatment comprises:
carrying out a chemical treatment using a process gas containing fluorocarbon to etch the tunnel barrier layer and the second magnetic layer overlying the tunnel barrier layer.

15. The method of claim 13 , wherein the protection layer comprises fluorine (F).

16. A method for fabricating a memory device, the method_comprising:
forming a magnetic tunneling junction (MTJ) stack of layers over a bottom electrode layer, wherein the MTJ stack of layers comprises a bottom magnetic layer, a tunnel barrier layer overlying the bottom magnetic layer, and a top magnetic layer overlying the tunnel barrier layer;
forming a top electrode layer over the MTJ stack of layers;
patterning the top electrode layer, the top magnetic layer and the tunnel barrier layer;
forming a protection layer over sidewalls of the top electrode layer, the top magnetic layer and the tunnel barrier layer, wherein the protection layer comprises carbon (C), hydrogen (H), and oxygen (O);
patterning the bottom magnetic layer and the bottom electrode layer to create conductive particles,
depositing the conductive particles on the protection layer, and
forming a cap dielectric layer over the conductive particles.

17. The method of claim 16 , wherein patterning the top electrode layer is carried out prior to patterning the top magnetic layer and the tunnel barrier layer.

18. The method of claim 16 , wherein patterning the top electrode layer and patterning the top magnetic layer and the tunnel barrier layer are carried out at the same time.

19. The method of claim 16 , Wherein patterning the top electrode layer, the top magnetic layer and the tunnel barrier layer is carried out by reactive ion etching.

20. The method of claim 16 , wherein the protection layer comprises fluorine (F).

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Jiann-Horng
• Li kun-yi
• Lin Han-Ting
• Lin Huan-Just
• Wang Chen-Jung
• Yang Sin-Yi

Classifications

• H10N50/10 Primary

  Magnetoresistive devices · CPC title

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• H10B61/00

  Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices · CPC title

• H10N50/01

  Manufacture or treatment · CPC title

• H10N50/80

  Constructional details · CPC title