Half-bridge circuit using separately packaged GaN power devices

Patent metadata

Field	Value
Publication number	US-11770010-B2
Application number	US-202218064209-A
Country	US
Kind code	B2
Filing date	Dec 9, 2022
Priority date	Sep 16, 2014
Publication date	Sep 26, 2023
Grant date	Sep 26, 2023

Abstract

GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Various embodiments of level shift circuits and their inventive aspects are disclosed.

First claim

What is claimed is:

1. A circuit, comprising:
a low-side circuit disposed on a first semiconductor die, the first semiconductor die formed from at least one layer of gallium-nitride disposed on a layer of silicon, wherein the low-side circuit comprises:
a low-side switch comprising a low-side switch control gate, a low-side source, and a low-side drain;
a low-side driver circuit coupled to the low-side switch control gate and arranged to control a conductivity state of the low-side switch in response to receiving a first input signal;
wherein the first semiconductor die is disposed within a first electronic package that includes a first die-attach pad attached to the first semiconductor die, a first external terminal electrically connected to the low-side source and a second external terminal electrically connected to the low-side drain; and

a high-side circuit disposed on a second semiconductor die, the second semiconductor die formed from at least one layer of gallium-nitride disposed on a layer of silicon, wherein the high-side circuit comprises:
a high-side switch comprising a high-side switch control gate, a high-side source, and a high-side drain; and
a high-side driver circuit coupled to the high-side switch control gate and arranged to control a conductivity state of the high-side switch in response to receiving a second input signal;
wherein the second semiconductor die is disposed within a second electronic package that includes a second die-attach pad attached to the second semiconductor die, a third external terminal electrically connected to the high-side source and a fourth external terminal electrically connected to the high-side drain;

wherein the low-side drain is electrically connected to the high-side source forming a half-bridge circuit.

2. The circuit of claim 1 wherein the first and second electronic packages are quad-flat no-lead electronic packages.

3. The circuit of claim 1 further comprising a first mold compound at least partially encapsulating the first semiconductor die and a second mold compound at least partially encapsulating the second semiconductor die.

4. The circuit of claim 1 wherein the at least one layer of gallium-nitride comprises a composite stack of III-nitride layers.

5. The circuit of claim 1 wherein the at least one layer of gallium-nitride comprises a layer of aluminum gallium nitride.

6. The circuit of claim 1 wherein the low-side switch and the high-side switch are each enhancement-mode transistors.

7. The circuit of claim 1 further comprising a level-shift circuit electrically coupled to the high-side driver circuit.

8. The circuit of claim 1 wherein the low-side drain and the high-side source are electrically connected through the second external terminal and the third external terminal.

9. A half-bridge circuit, comprising:
a low-side circuit disposed on one or more gallium-nitride layers of a first semiconductor device, wherein the low-side circuit comprises:
a low-side transistor comprising a low-side transistor control gate, a low-side source, and
a low-side drain wherein the low-side transistor is controlled by a low-side transistor driver circuit arranged to change a conductivity state of the low-side transistor in response to receiving a first input signal;
wherein the first semiconductor device is disposed within a first electronic package that includes a first die-attach pad attached to the first semiconductor device, a first external terminal electrically connected to the low-side source, and a second external terminal electrically coupled to the low-side drain; and

a high-side circuit disposed on one or more gallium-nitride layers of a second semiconductor device, wherein the high-side circuit comprises:
a high-side transistor comprising a high-side transistor control gate, a high-side source, and a high-side drain wherein the high-side transistor is controlled by a high-side transistor driver circuit arranged to change a conductivity state of the high-side transistor in response to receiving a second input signal;
wherein the second semiconductor device is disposed within a second electronic package that includes a second die-attach pad attached to the second semiconductor device, a third external terminal electrically connected to the high-side source and a fourth external terminal electrically connected to the high-side drain;

wherein the low-side drain is electrically connected to the high-side source forming a switch node of the half-bridge circuit.

10. The half-bridge circuit of claim 9 wherein the first and second electronic packages are quad-flat no-lead electronic packages.

11. The half-bridge circuit of claim 9 wherein the one or more gallium-nitride layers comprises a composite stack of III-nitride layers.

12. The half-bridge circuit of claim 9 wherein the low-side transistor and the high-side transistor are each enhancement-mode transistors.

13. The half-bridge circuit of claim 9 further comprising a level-shift circuit electrically coupled to the high-side transistor driver circuit.

14. The half-bridge circuit of claim 9 wherein the low-side drain and the high-side source are electrically connected through the second external terminal and the third external terminal.

15. The half-bridge circuit of claim 9 wherein the low-side transistor driver circuit is disposed on the first semiconductor device.

16. The half-bridge circuit of claim 9 wherein the low-side transistor driver circuit is disposed on a third semiconductor device.

17. The half-bridge circuit of claim 9 wherein the high-side transistor driver circuit is disposed on the second semiconductor device.

18. The half-bridge circuit of claim 9 wherein the high-side transistor driver circuit is disposed on a third semiconductor device.

19. A half-bridge power converter, comprising:
a low-side circuit disposed on a first semiconductor device, the first semiconductor device formed from a first semiconductor substrate comprising gallium-nitride, wherein the low-side circuit comprises:
a low-side transistor including a low-side switch control gate, a low-side source, and a low-side drain wherein the low-side transistor is controlled by a low-side transistor driver circuit arranged to control a conductivity state of the low-side transistor in response to receiving a first input signal;
wherein the first semiconductor device is attached to a first die-attach pad, the low-side source is electrically connected to a first external terminal, and the low-side drain is electrically connected to a second external terminal; and

a high-side circuit disposed on a second semiconductor device, the second semiconductor device formed from a second semiconductor substrate comprising gallium-nitride, wherein the high-side circuit comprises:
a high-side transistor including a high-side switch control gate, a high-side source, and a high-side drain wherein the high-side transistor is controlled by a high-side transistor driver circuit arranged to control a conductivity state of the high-side transistor in response to receiving a second input signal;
wherein the second semiconductor device is attached to a second die-attach pad, the high-side source is electrically connected to a third external terminal and the high-side drain is electrically connected to a fourth external terminal;

wherein the low-side drain is electrically connected to the high-side source forming a switch-node of the half-bridge power converter.

20. The half-bridge power converter of claim 19 wherein t

Assignees

• Navitas Semiconductor Ltd

Inventors

• Kinzer Daniel M
• Sharma Santosh
• Zhang Ju Jason

Classifications

• H10W90/811

  Multiple chips on leadframes · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/481

  for devices being provided for in groups H10D8/00 - H10D48/00 · CPC title

• H10W70/411 Primary

  Chip-supporting parts, e.g. die pads · CPC title

• H10W42/80

  protecting against overcurrent or overload, e.g. fuses or shunts (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title