Detection of laser-based security attacks

Patent metadata

Field	Value
Publication number	US-11769740-B2
Application number	US-202117494747-A
Country	US
Kind code	B2
Filing date	Oct 5, 2021
Priority date	Mar 20, 2019
Publication date	Sep 26, 2023
Grant date	Sep 26, 2023

Abstract

Various embodiments include integrated approaches to detecting attempts to breach system-level or chip-level security using photo-generated currents induced by lasers or other radiation sources. Various embodiments integrate photo-detection circuits with a secure processor or other circuit in such a manner that the response to a security attack is fast enough to prevent loss of secure or private information are described. Various embodiments include circuits capable of providing a permanent record of photocurrent detection.

First claim

What is claimed is:

1. A method of detecting an incident of radiation on a photocurrent detection circuit, comprising:
determining whether a change in logic state of a logic circuit occurs indicating that a photocurrent is induced on the photocurrent detection circuit by radiation, wherein the photocurrent detection circuit comprises:
a first N-type metal-oxide-semiconductor (MOS) device electrically connected to a first P-type MOS device to form the logic circuit, wherein the logic circuit is an inverter; and
an inverting buffer, wherein an input of the inverting buffer is coupled to an output of the inverter;

determining that the photocurrent induced by radiation exists in response to determining that a change in the logic state of the logic circuit occurred; and
performing a countermeasure in response to determining that the photocurrent induced by radiation exists, wherein the countermeasure comprises disabling buffers in clock or data paths due to the photocurrent induced by radiation.

2. The method of claim 1 , further comprising:
resetting the photocurrent detection circuit to pre-charge the output of the inverter to a logic high voltage, wherein detecting the change in logic state of the logic circuit comprises:
detecting a change in an output of the inverting buffer.

3. The method of claim 1 , wherein the photocurrent detection circuit further comprises:
an additional NMOS device, wherein a gate of the additional NMOS device is coupled to a gate of the first NMOS device, a source of the additional NMOS device is coupled to an output of the inverter, and a drain of the additional NMOS device is coupled to ground.

4. The method of claim 3 , further comprising:
biasing the output of the logic circuit to a bias current such that the output of the logic circuit is a logic high voltage level in an absence of the incident of radiation.

5. The method of claim 3 , wherein the photocurrent detection circuit further comprises:
an additional PMOS device, wherein a gate of the additional PMOS device is coupled to a gate of the first PMOS device, a drain of the additional PMOS device is coupled to an output of the inverter, and a source of the additional PMOS device is coupled to logic high voltage.

6. The method of claim 5 , further comprising:
biasing the output of the logic circuit to a bias current such that the output of the logic circuit is a logic high voltage level in an absence of the incident of radiation.

Assignees

• Qualcomm Inc

Inventors

• Lewis Alan
• Fu Zhengming
• Chen Nan
• Polak Adam
• Fuentes Laura
• Bullard Gregory
• Todorovich Mark

Classifications

• H10W42/405 Primary

  using active circuits · CPC title

• H10F39/103

  the at least one element covered by H10F30/00 having potential barriers, e.g. integrated devices comprising photodiodes or phototransistors · CPC title

• H01L23/576 Primary

  Electricity · mapped topic

• G06F21/755

  with measures against power attack · CPC title

• H01L27/1443

  Electricity · mapped topic