Detection of laser-based security attacks

Patent metadata

Field	Value
Publication number	US-11145608-B2
Application number	US-201916359319-A
Country	US
Kind code	B2
Filing date	Mar 20, 2019
Priority date	Mar 20, 2019
Publication date	Oct 12, 2021
Grant date	Oct 12, 2021

Abstract

Various embodiments include integrated approaches to detecting attempts to breach system-level or chip-level security using photo-generated currents induced by lasers or other radiation sources. Various embodiments integrate photo-detection circuits with a secure processor or other circuit in such a manner that the response to a security attack is fast enough to prevent loss of secure or private information are described. Various embodiments include circuits capable of providing a permanent record of photocurrent detection.

First claim

What is claimed is:

1. A photocurrent detection circuit, comprising:
a first N-type metal-oxide-semiconductor (first NMOS) device electrically connected to a first P-type MOS (first PMOS) device to form a logic circuit, wherein the logic circuit is a complementary metal oxide semiconductor (CMOS) inverter, and wherein the first NMOS device and the first PMOS device are asymmetrically sized and configured such that a change in a logic state output of the logic circuit indicates a photocurrent induced by radiation;
a low voltage NMOS device coupled to an output of the CMOS inverter, wherein the first PMOS device is a high voltage device and the first NMOS device is a high voltage device; and
a capacitor coupled to the output of the logic circuit and a gate of the low voltage NMOS device.

2. The photocurrent detection circuit of claim 1 , wherein the first NMOS device is larger than the first PMOS device.

3. The photocurrent detection circuit of claim 1 , wherein a drain of an additional NMOS device is coupled to an output of the CMOS inverter and a source of the additional NMOS device is coupled to ground.

4. The photocurrent detection circuit of claim 3 , wherein a gate of the additional NMOS device is coupled to ground.

5. The photocurrent detection circuit of claim 3 , further comprising:
an output buffer, wherein an input of the output buffer is coupled to the drain of the additional NMOS device.

6. The photocurrent detection circuit of claim 5 , wherein a first photodetector circuit comprises the CMOS inverter, the additional NMOS device and the output buffer, the photocurrent detection circuit further comprising:
a second photodetector circuit comprising:
a second CMOS inverter formed by coupling a gate of a second NMOS device with a gate of a second PMOS device, and coupling a drain of the second PMOS device to a drain of the second NMOS device to form an output of the second CMOS inverter;
a second additional NMOS device, wherein a drain of the second additional NMOS device is coupled to the output of the second CMOS inverter and a source of the second additional NMOS device is coupled to ground; and
a second output buffer, wherein an input of the second output buffer is coupled to the drain of the second additional NMOS device;
wherein the input of the second photodetector circuit is coupled to the output of the first photodetector circuit.

7. The photocurrent detection circuit of claim 6 , further comprising:
a third photodetector circuit comprising:
a third CMOS inverter formed by coupling a gate of a third NMOS device with a gate of a third PMOS device, and coupling a drain of the second PMOS device to a drain of the second NMOS device to form an output of the third CMOS inverter;
a third additional PMOS device, wherein a drain of the third additional PMOS device is coupled to the output of the third CMOS inverter and a source of the third additional PMOS device is coupled to a logic high voltage; and
a third output buffer, wherein an input of the third output buffer is coupled to the drain of the third additional PMOS device;
wherein the input of the third photodetector circuit is coupled to the output of the second photodetector circuit.

8. The photocurrent detection circuit of claim 1 , further comprising:
the low voltage NMOS device coupled to an output of the CMOS inverter, wherein the first PMOS device and the first NMOS device are high voltage devices, and wherein the first PMOS device is larger than the first NMOS device;
a second PMOS device, wherein a gate of the second PMOS device is coupled to a source of the second PMOS device and the gate and the source of the second PMOS device are coupled to high voltage, wherein the second PMOS device is a high voltage device and is symmetrically sized to the first PMOS device; and
a second NMOS device, wherein a gate of the second NMOS device is coupled to low voltage, a drain of the second NMOS device is coupled to a source of the first NMOS device and a source of the second NMOS device is coupled to ground, wherein the second NMOS device is a high voltage device and is symmetrically sized to the first NMOS device.

9. The photocurrent detection circuit of claim 8 , further comprising:
a current limited buffer, wherein an output of the current limited buffer is coupled to the gate of the second PMOS device; and
the capacitor configured between the output of the current limited buffer and ground.

Assignees

• Qualcomm Inc

Inventors

• Lewis Alan
• Fu Zhengming
• Chen Nan
• Polak Adam
• Fuentes Laura
• Bullard Gregory
• Todorovich Mark

Classifications

• H10W42/405 Primary

  using active circuits · CPC title

• H10F39/103

  the at least one element covered by H10F30/00 having potential barriers, e.g. integrated devices comprising photodiodes or phototransistors · CPC title

• G06F21/75 Primary

  by inhibiting the analysis of circuitry or operation · CPC title

• G06F21/755

  with measures against power attack · CPC title

• Y04S40/20

  Information technology specific aspects, e.g. CAD, simulation, modelling, system security · CPC title