Timing controller, display device, and signal adjustment method

Patent metadata

Field	Value
Publication number	US-11769467-B2
Application number	US-202117424132-A
Country	US
Kind code	B2
Filing date	Jan 11, 2021
Priority date	Jan 13, 2020
Publication date	Sep 26, 2023
Grant date	Sep 26, 2023

Abstract

A timing controller includes a receiving circuit, a timing control circuit, and a plurality of insertion loss circuits. The receiving circuit is configured to receive N frames of signals. The timing control circuit is configured to: detect a bit error rate of an (M-1)th-frame signal in a blanking interval of an Mth-frame signal; adjust a swing of the (M-1)th-frame signal according to a target swing value corresponding to the bit error rate of the (M-1)th-frame signal; and select the corresponding insertion loss circuit according to the target swing value corresponding to the bit error rate of the (M-1)th-frame signal, wherein M and N are both positive integers, and M is greater than 1 and less than or equal to N. The present disclosure is applied to signal adjustment of the timing controller.

First claim

The invention claimed is:

1. A timing controller, wherein the timing controller comprises a receiving circuit, a timing control circuit, and a plurality of insertion loss circuits;
the receiving circuit and the insertion loss circuit are respectively connected to the timing control circuit;
the receiving circuit is configured to receive N frames of signals;
the timing control circuit is configured to:
detect a bit error rate of an (M−1) th -frame signal in a blanking interval of an Mth-frame signal;
adjust a swing of the (M−1) th -frame signal according to a target swing value corresponding to the bit error rate of the (M−1) th -frame signal; and
select the corresponding insertion loss circuit according to the target swing value corresponding to the bit error rate of the (M−1) th -frame signal to consume energy generated when adjusting the swing of the (M−1) th -frame signal;
wherein M and N are both positive integers, and M is greater than 1 and less than or equal to N.

2. The timing controller according to claim 1 , wherein the adjusting a swing of the (M−1) th -frame signal according to a target swing value corresponding to the bit error rate of the (M−1) th -frame signal comprises:
determining a bit error rate interval where the bit error rate of the (M−1) th -frame signal belongs; and
adjusting the swing of the (M−1) th -frame signal according to a corresponding relationship between the bit error rate interval and the target swing value.

3. The timing controller according to claim 2 , wherein the adjusting the swing of the (M−1) th -frame signal according to a corresponding relationship between the bit error rate interval and the target swing value in a swing regulation table comprises:
determining, by the timing control circuit according to the corresponding relationship between the bit error rate interval and the target swing value in the swing regulation table, the target swing value corresponding to the bit error rate of the (M−1) th -frame signal; and
adjusting a swing value of the (M−1) th -frame signal as the target swing value corresponding to the bit error rate of the (M−1) th -frame signal.

4. The timing controller according to claim 3 , wherein the timing control circuit is further configured to:
store the swing regulation table before the blanking interval of a first-frame signal, wherein the swing regulation table comprises a plurality of bit error rate intervals, a plurality of target swing values, and the corresponding relationship between the bit error rate interval and the target swing value.

5. The timing controller according to claim 2 , wherein the relationship between the bit error rate interval and the target swing value is stored in a swing regulation table.

6. The timing controller according to claim 1 , wherein the plurality of insertion loss circuits are divided into a plurality of groups of insertion loss units, each group of the insertion loss units comprise a first insertion loss circuit and a second insertion loss circuit, the first insertion loss circuit is configured to consume a signal having a first frequency, and the second insertion loss circuit is configured to consume a signal having a second frequency, wherein the first frequency is smaller than the second frequency.

7. The timing controller according to claim 6 , wherein the target swing value is corresponding to the insertion loss units one to one.

8. The timing controller according to claim 6 , wherein in the each group of the insertion loss units, the first insertion loss circuit comprises: a capacitor, a first switch, a first ground terminal, and a second ground terminal; two terminals of the capacitor are respectively connected to the first ground terminal and a first terminal of the first switch, and a second terminal of the first switch is connected to the second ground terminal; and
the second insertion loss circuit comprises: a bead, a second switch, a third ground terminal, and a fourth ground terminal; and two terminals of the bead are respectively connected to the third ground terminal and a first terminal of the second switch, and a second terminal of the second switch is connected to the fourth ground terminal.

9. The timing controller according to claim 8 , wherein the first ground terminals of the plurality of first insertion loss circuits and the third ground terminals of the plurality of second insertion loss circuits are the same ground terminals, and the second ground terminals of the plurality of first insertion loss circuits and the fourth ground terminals of the plurality of second insertion loss circuits are the same ground terminals.

10. A display device, wherein the device comprises the timing controller according to claim 1 .

11. A signal adjustment method, applied to the timing controller according to claim 1 , the timing controller comprising a receiving circuit and a plurality of insertion loss circuits, the receiving circuit being configured to receive N frames of signals, wherein the method comprises:
detecting a bit error rate of an (M−1) th -frame signal in a blanking interval of an M th -frame signal;
adjusting a swing of the (M−1) th -frame signal according to a target swing value corresponding to the bit error rate of the (M−1) th -frame signal; and
selecting the corresponding insertion loss circuit according to the target swing value corresponding to the bit error rate of the (M−1) th -frame signal to consume energy generated when adjusting the swing of the (M−1) th -frame signal;
wherein M and N are both positive integers, and M is greater than 1 and less than N.

12. The signal adjustment method according to claim 11 , wherein the adjusting a swing of the (M−1) th -frame signal according to a target swing value corresponding to the bit error rate of the (M−1) th -frame signal comprises:
determining a bit error rate interval where the bit error rate of the (M−1) th -frame signal belongs; and
adjusting the swing of the (M−1) th -frame signal according to a corresponding relationship between the bit error rate interval and the target swing value.

13. The signal adjustment method according to claim 12 , wherein the adjusting the swing of the (M−1) th -frame signal according to a corresponding relationship between the bit error rate interval and the target swing value comprises:
determining the target swing value corresponding to the bit error rate of the (M−1) th -frame signal according to the corresponding relationship between the bit error rate interval and the target swing value in the swing regulation table; and
adjusting a swing value of the (M−1) th -frame signal as the target swing value corresponding to the bit error rate of the (M−1) th -frame signal.

14. The signal adjustment method according to claim 12 , wherein before the blanking interval of a first-frame signal, the method further comprises:
storing the swing regulation table, wherein the swing regulation table comprises a plurality of bit error rate intervals, a plurality of target swing values, and the corresponding relationship between the bit error rate interval and the target swing value.

15. The signal adjustment method according to claim 11 , wherein the blanking interval of the M th -frame signal comprises an initial interval, an intermediate interval, and an end interval; and
the detecting a bit error rate of an (M−1) th -frame signal in a blanking interval of an M th -frame signal comprises:
detecting the bit error rate of the (M−1) th -frame signal in the intermediate interval of the blanking interval of the M th -frame signal.

16. A non transitory computer-readable

Assignees

• Hefei Xinsheng Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Liu Yuanyuan
• Qiao Xuanxuan
• Liu Shuai
• Yuan Xianfeng
• Chen Zejun
• Wang Jianjun
• Xing Zhenzhou

Classifications

• G09G5/18 Primary

  Timing circuits for raster scan displays (specially adapted for television H04N {; synchronisation between the display unit and other display units, videodisc player G09G5/12}) · CPC title

• G09G3/2022 Primary

  using sub-frames · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G5/003 Primary

  Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto (specific for a CRT G09G1/165; for a flat panel G09G3/2092) · CPC title

• G09G3/2092

  Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165) · CPC title