Driving circuit, driving method thereof and display device

Patent metadata

Field	Value
Publication number	US-2016372084-A1
Application number	US-201514908327-A
Country	US
Kind code	A1
Filing date	Sep 16, 2015
Priority date	Jan 26, 2015
Publication date	Dec 22, 2016
Grant date	—

Abstract

Embodiments of the present invention provide a driving circuit, a driving method thereof and a display device. The driving circuit includes a timing controller, a timing adjustor and a driver, wherein the timing controller outputs first data signal and first clock signal, the timing adjustor adjusts phases of first data signal and first clock signal, so as to generate second data signal and second clock signal corresponding to each other, and the driver generates driving signal based on second data signal and second clock signal. The timing adjustor actively adjusts first data signal and first clock signal output from the timing controller, so as to generate second data signal and second clock signal corresponding to each other and actually needed by the driver, thereby realizing a perfect match with a display panel, which in turn improves display quality of a display device.

First claim

1 . A driving circuit, which includes a timing controller, a timing adjustor and a driver, the timing adjustor being connected with an output of the timing controller, and an output of the timing adjustor being connected with the driver, wherein
the timing controller is configured to output a first data signal and a first clock signal; the timing adjustor is configured to adjust phases of the first data signal and the first clock signal, so as to generate a second data signal and a second clock signal corresponding to each other; and the driver is configured to generate a driving signal based on the second data signal and the second clock signal.

2 . The driving circuit according to claim 1 , wherein the timing adjustor includes a conversion unit and a synchronization unit, an input of the conversion unit being connected with the timing controller, a first output of the conversion unit being connected with a first input of the synchronization unit, a second output of the conversion unit being connected with the driver, a second input of the synchronization unit being connected with the timing controller, and an output of the synchronization unit being connected with the driver; and wherein
the conversion unit is configured to adjust the phase of the first clock signal, so as to generate the second clock signal; and the synchronization unit is configured to adjust the phase of the first data signal based on the second clock signal, so as to generate the second data signal, the second data signal and the second clock signal having a predetermined phase difference therebetween.

3 . The driving circuit according to claim 2 , wherein the conversion unit includes a plurality of delay circuits.

4 . The driving circuit according to claim 3 , wherein the delay circuit includes an inverter.

5 . The driving circuit according to claim 4 , wherein the inverter is selected from a NMOS-type inverter, a PMOS-type inverter and a CMOS-type inverter.

6 . The driving circuit according to claim 2 , wherein the synchronization unit includes a D flip-flop.

7 . The driving circuit according to claim 1 , wherein the driver includes a source driver.

8 . The driving circuit according to claim 1 , wherein the driver and the timing adjustor are provided integrally.

9 . A display device, which includes a display panel and the driving circuit according to claim 1 .

10 . A driving method for a driving circuit including a timing controller, a timing adjustor and a driver, the timing adjustor being connected with an output of the timing controller, and an output of the timing adjustor being connected with the driver, the driving method including:
outputting a first data signal and a first clock signal by the timing controller; adjusting phases of the first data signal and the first clock signal by the timing adjustor, so as to generate a second data signal and a second clock signal corresponding to each other; and generating a driving signal by the driver based on the second data signal and the second clock signal.

11 . The driving method for the driving circuit according to claim 10 , wherein the timing adjustor includes a conversion unit and a synchronization unit, an input of the conversion unit being connected with the timing controller, a first output of the conversion unit being connected with a first input of the synchronization unit, a second output of the conversion unit being connected with the driver, a second input of the synchronization unit being connected with the timing controller, and an output of the synchronization unit being connected with the driver; and wherein
the step of adjusting phases of the first data signal and the first clock signal by the timing adjustor, so as to generate a second data signal and a second clock signal corresponding to each other includes: adjusting the phase of the first clock signal by the conversion unit, so as to generate the second clock signal; adjusting the phase of the first data signal by the synchronization unit based on the second clock signal, so as to generate the second data signal, the second data signal and the second clock signal having a predetermined phase difference therebetween.

12 . The driving method for the driving circuit according to claim 11 , wherein the conversion unit includes a plurality of delay circuits.

13 . The driving method for the driving circuit according to claim 12 , wherein the delay circuit includes an inverter.

14 . The driving method for the driving circuit according to claim 13 , wherein the inverter is selected from a NMOS-type inverter, a PMOS-type inverter and a CMOS-type inverter.

15 . The driving method for the driving circuit according to claim 11 , wherein the synchronization unit includes a D flip-flop.

16 . The driving method for the driving circuit according to claim 10 , wherein the driver includes a source driver.

17 . The driving method for the driving circuit according to claim 10 , wherein the driver and the timing adjustor are provided integrally.

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Display Tech Co

Inventors

• Wang Jieqiong

Classifications

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2370/08

  Details of image data interface between the display device controller and the data line driver circuit · CPC title

• G09G3/20

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G5/18 Primary

  Timing circuits for raster scan displays (specially adapted for television H04N {; synchronisation between the display unit and other display units, videodisc player G09G5/12}) · CPC title

• G09G3/2092 Primary

  Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165) · CPC title