Flattening portal bridge

Patent metadata

Field	Value
Publication number	US-11768791-B2
Application number	US-202217734733-A
Country	US
Kind code	B2
Filing date	May 2, 2022
Priority date	Mar 4, 2016
Publication date	Sep 26, 2023
Grant date	Sep 26, 2023

Abstract

A flattening portal bridge (FPB) is provided to support addressing according to a first addressing scheme and a second, alternative addressing scheme. The FPB comprises a primary side and a secondary side, the primary side connects to a first set of devices addressed according to a first addressing scheme, and the secondary side connects to a second set of devices addressed according to a second addressing scheme. The first addressing scheme uses a unique bus number within a Bus/Device/Function (BDF) address space for each device in the first set of devices, and the second bus addressing scheme uses a unique bus-device number for each device in the second set of devices.

First claim

The invention claimed is:

1. At least one non-transitory machine accessible storage medium having instructions stored thereon, the instructions when executed on a machine, cause the machine to:
assign an address to each of a plurality of devices in a system; and
determine whether to assign the address according to a first addressing scheme or a second addressing scheme, wherein the first addressing scheme is to assign a unique bus number within a Bus/Device/Function (BDF) address space to each device addressed in the first addressing scheme and the second addressing scheme is to assign a unique bus-device number within the BDF address space, wherein a Flattening Portal Bridge (FPB) is to decode at least one Transaction Layer Packet (TLP) to determine whether to associate the TLP with a primary side of the FPB or a secondary side of the FPB.

2. The non-transitory storage medium of claim 1 , wherein at least one bus number is to be reused to address two or more devices in the second addressing scheme.

3. The non-transitory storage medium of claim 1 , wherein assigning the address comprises designating a range of bus numbers in the BDF address space to be used to address devices according to the second addressing scheme.

4. The non-transitory storage medium of claim 3 , wherein the range of bus numbers is associated with a switch and the bus numbers in the range of bus numbers are used in the bus-device numbers to be assigned to each device connected to the switch.

5. The non-transitory storage medium of claim 4 , wherein the devices connected to the switch comprise a segment.

6. The non-transitory storage medium of claim 1 , wherein the address comprises a configuration address.

7. The non-transitory storage medium of claim 1 , wherein the BDF address space comprises a Peripheral Component Interconnect (PCI) based address space.

8. The non-transitory storage medium of claim 7 , wherein each bus-device number comprises an eight bit bus number and a five bit device number.

9. An apparatus comprising:
a flattening portal bridge (FPB) having a primary side and a secondary side, wherein the primary side is to couple to a first set of devices addressed according to a first addressing scheme and the secondary side is to couple to a second set of devices addressed according to a second addressing scheme;
wherein the FPB is to determine whether to route a packet on the primary side or the secondary side based on address information in the packet, wherein the first addressing scheme is to utilize a unique bus number within a Bus/Device/Function (BDF) address space for each device in the first set of devices and the second addressing scheme is to utilize a unique bus-device number in the BDF space for each device in the second set of devices.

10. The apparatus of claim 9 , wherein respective bus-device numbers, assigned to a plurality of devices in the second set of devices, each comprise a bus number and a different device number.

11. The apparatus of claim 9 , wherein the primary addressing scheme comprises a legacy addressing scheme.

12. The apparatus of claim 9 , wherein the BDF addressing space comprises a Peripheral Component Interconnect Express (PCIe) configuration space.

13. The apparatus of claim 9 , further comprising a plurality of ports, wherein a first port from the plurality of ports comprises the FPB and at least one other port from the plurality of ports comprises a different FPB.

14. The apparatus of claim 13 , wherein the plurality of ports comprises at least one port without an FPB.

15. The apparatus of claim 13 , further comprising a switch, wherein the switch comprises the plurality of ports.

16. The apparatus of claim 13 , further comprising a root complex, wherein the root complex comprises the plurality of ports.

17. A system comprising:
a flattening portal bridge (FPB) having a primary side and a secondary side, wherein the primary side is to couple to a first set of devices addressed according to a first addressing scheme and the secondary side is to couple to a second set of devices addressed according to a second addressing scheme; and
a switch including a plurality of ports, wherein a first port from the plurality of ports comprises the FPB,
wherein the FPB is to determine whether to route a packet on the primary side or the secondary side based on address information in the packet, wherein the first addressing scheme is to utilize a unique bus number within a Bus/Device/Function (BDF) address space for each device in the first set of devices and the second addressing scheme is to utilize a unique bus-device number in the BDF space for each device in the second set of devices.

18. The system of claim 17 , further comprising a capability register to be encoded to selectively enable support for the secondary addressing scheme on a port of the switch.

19. The system of claim 17 , wherein the switch device comprises a root complex.

20. The system of claim 19 , wherein the root complex comprises the plurality of ports.

Assignees

• Intel Corp

Inventors

• Harriman David J
• Rozic Reuven
• Dan Maxim
• Sethi Prashant
• Gough Robert E
• Rabindranath Shanthanand Kutuva

Classifications

• G06F13/404 Primary

  with address mapping · CPC title

• G06F13/4022 Primary

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F13/4068

  Electrical coupling · CPC title

• G06F13/4221

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title