Data bus duty cycle distortion compensation

Patent metadata

Field	Value
Publication number	US-11768782-B2
Application number	US-202217880226-A
Country	US
Kind code	B2
Filing date	Aug 3, 2022
Priority date	Oct 30, 2020
Publication date	Sep 26, 2023
Grant date	Sep 26, 2023

Abstract

An electrical circuit device includes a signal bus comprising a plurality of parallel signal paths and a calibration circuit, operatively coupled with the signal bus. The calibration circuit can perform operations including determining a representative duty cycle for a plurality of signals transferred via the plurality of parallel signal paths, the plurality of signals comprising a plurality of duty cycles and comparing the representative duty cycle for the plurality of signals transferred via the plurality of parallel signal paths to a reference value to determine a comparison result. The calibration circuit can perform further operations including adjusting, based on the comparison result, a trim value associated with the plurality of duty cycles of the plurality of signals to compensate for distortion in the plurality of duty cycles and calibrating the plurality of duty cycles of the plurality of signals using the adjusted trim value.

First claim

What is claimed is:

1. An electrical circuit device comprising:
a signal bus comprising a plurality of parallel signal paths; and
a calibration circuit, operatively coupled with the signal bus, the calibration circuit comprising:
a first circuit coupled to the plurality of parallel signal paths, the first circuit to determine a representative duty cycle for a plurality of duty cycles of a plurality of signals transferred via the plurality of parallel signal paths, and to determine whether the representative duty cycle is greater than or less than a reference value; and
a second circuit coupled to first circuit, the second circuit to calibrate the plurality of duty cycles of the plurality of signals based on whether the representative duty cycle is greater than or less than the reference value.

2. The electrical circuit device of claim 1 , wherein the first circuit comprises a multiple inputs integrator circuit comprising a plurality of passive low pass filters coupled to the plurality of parallel signal paths, the plurality of passive low pass filters to obtain a plurality of direct current (DC) level representations of the plurality of duty cycles of the plurality of signals, and wherein an output of the multiple inputs integrator circuit comprises a DC level representation for the plurality of DC level representations.

3. The electrical circuit device of claim 2 , wherein the first circuit further comprises a comparator circuit to convert the DC level representation into a representative digital signal representation, and to determine whether the representative duty cycle is greater than or less than a reference value, the comparator circuit is to compare the DC level representation to the reference value.

4. The electrical circuit device of claim 1 , wherein the representative duty cycle for the plurality of duty cycles of the plurality of signals transferred via the plurality of parallel signal paths comprises an average of the plurality of duty cycles, and wherein the reference value comprises one half of a voltage supply level.

5. The electrical circuit device of claim 1 , wherein the second circuit comprises a decoder circuit to convert a trim value associated with the plurality of duty cycles of the plurality of signals into one or more biasing voltages and/or biasing currents and apply the one or more biasing voltages and/or biasing currents to the plurality of signals transferred via the plurality of parallel signal paths to calibrate the plurality of duty cycles.

6. The electrical circuit device of claim 1 , further comprising:
a memory array, wherein the signal bus comprising the plurality of parallel signal paths is coupled to the memory array.

7. The electrical circuit device of claim 1 , wherein distortion in the plurality of duty cycles is based at least in part on processing variations in components that form the plurality of parallel signal paths.

8. An electrical circuit device comprising:
a signal bus comprising a plurality of parallel signal paths; and
a calibration circuit, operatively coupled with the signal bus, to perform operations comprising:
determining representative duty cycle for a plurality of duty cycles of a plurality of signals transferred via the plurality of parallel signal paths;
determining whether the representative duty cycle is greater than or less than a reference value; and
calibrating the plurality of duty cycles of the plurality of signals based on whether the representative duty cycle is greater than or less than the reference value.

9. The electrical circuit device of claim 8 , wherein the calibration circuit is to perform operations further comprising:
obtaining, using a plurality of passive low pass filters, a plurality of direct current (DC) level representations of the plurality of duty cycles of the plurality of signals;
determining a DC level representation for the plurality of DC level representations; and
converting, using a comparator, the DC level representation into a representative digital signal representation.

10. The electrical circuit device of claim 9 , wherein determining whether the representative duty cycle is greater than or less than the reference value comprises comparing, using the comparator, the DC level representation to the reference value.

11. The electrical circuit device of claim 8 , wherein the representative duty cycle for the plurality of duty cycles of the plurality of signals transferred via the plurality of parallel signal paths comprises an average of the plurality of duty cycles, and wherein the reference value comprises one half of a voltage supply level.

12. The electrical circuit device of claim 8 , wherein the calibration circuit is to perform operations further comprising:
converting a trim value associated with the plurality of duty cycles of the plurality of signals into one or more biasing voltages and/or biasing currents; and
calibrating the plurality of duty cycles by applying the one or more biasing voltages and/or biasing currents to the plurality of signals transferred via the plurality of parallel signal paths.

13. The electrical circuit device of claim 8 , further comprising:
a memory array, wherein the signal bus comprising the plurality of parallel signal paths is coupled to the memory array.

14. The electrical circuit device of claim 8 , wherein distortion in the plurality of duty cycles is based at least in part on processing variations in components that form the plurality of parallel signal paths.

15. A method comprising:
determining representative duty cycle for a plurality of duty cycles of a plurality of signals transferred via a plurality of parallel signal paths;
determining whether the representative duty cycle is greater than or less than a reference value; and
calibrating the plurality of duty cycles of the plurality of signals based on whether the representative duty cycle is greater than or less than the reference value.

16. The method of claim 15 , further comprising:
obtaining, using a plurality of passive low pass filters, a plurality of direct current (DC) level representations of the plurality of duty cycles of the plurality of signals;
determining a DC level representation for the plurality of DC level representations; and
converting, using a comparator, the DC level representation into a representative digital signal representation.

17. The method of claim 16 , wherein determining whether the representative duty cycle is greater than or less than the reference value comprises comparing, using the comparator, the DC level representation to the reference value.

18. The method of claim 15 , wherein the representative duty cycle for the plurality of duty cycles of the plurality of signals transferred via the plurality of parallel signal paths comprises an average of the plurality of duty cycles, and wherein the reference value comprises one half of a voltage supply level.

19. The method of claim 15 , further comprising:
converting a trim value associated with the plurality of duty cycles of the plurality of signals into one or more biasing voltages and/or biasing currents; and
calibrating the plurality of duty cycles by applying the one or more biasing voltages and/or biasing currents to the plurality of signals transferred via the plurality of parallel signal paths.

20. The method of claim 15 , wherein distortion in the plurality of duty cycles is based at least in part on processing variations in components that form the plurality of parallel signal paths.

Assignees

• Micron Technology Inc

Inventors

• Wang Guan
• Ghalam Ali Feiz Zarrin
• Chen Chin-Yu
• Kim Jongin

Classifications

• G06F13/1668 Primary

  Details of memory controller · CPC title

• G11C16/32

  Timing circuits · CPC title

• H03K3/017

  Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C7/22 Primary

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title