Internal clock distortion calibration using DC component offset of clock signal

Patent metadata

Field	Value
Publication number	US-10270429-B1
Application number	US-201715848796-A
Country	US
Kind code	B1
Filing date	Dec 20, 2017
Priority date	Dec 20, 2017
Publication date	Apr 23, 2019
Grant date	Apr 23, 2019

Abstract

Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes an electrical circuit die having clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to compare a first duty cycle of a first voltage signal of the clock signal to a second duty cycle of a second voltage signal of the clock signal. Based on the comparison, the clock calibration circuitry is configured to adjust a trim value associated with at least one of the first and the second duty cycles of the first and the second voltage signals, respectively, to calibrate at least one of the first and the second duty cycles and account for duty cycle distortion encountered as the clock signal propagates through a clock tree of the electrical circuit device.

First claim

We claim:

1. A semiconductor device comprising clock distortion calibration circuitry configured to:
compare a first duty cycle of a first voltage signal of a clock signal to a second duty cycle of a second voltage signal of the clock signal that is complementary to the first voltage signal,
based on the comparison, adjust a trim value associated with the first and the second duty cycles of the first and the second voltage signals to adjust the first duty cycle and the second duty cycle to the average of the first duty cycle and the second duty cycle, and
calibrate at least one of the first and the second duty cycles of the first and the second voltage signals using the adjusted trim value.

2. The semiconductor device of claim 1 , wherein the clock distortion calibration circuitry is further configured to:
obtain, using a first low pass filter, a first direct current (dc) level representation of the first duty cycle;
obtain, using a second low pass filter, a second dc level representation of the second duty cycle; and
convert, using a comparator, the first and the second dc level representations into a first digital signal representation and a second digital signal representation, respectively.

3. The semiconductor device of claim 2 , wherein the clock distortion calibration circuitry is configured to compare the first duty cycle to the second duty cycle by comparing, using the comparator, the first digital signal representation to the second digital signal representation.

4. The semiconductor device of claim 1 , wherein the clock distortion calibration circuitry is configured to adjust the trim value using a state machine.

5. The semiconductor device of claim 1 , wherein the clock distortion calibration circuitry is further configured to (1) convert the trim value into one or more biasing voltages and/or biasing currents and (2) calibrate at least one of the first and the second duty cycles by applying the one or more biasing voltages and/or biasing currents to at least one of a corresponding first input buffer and a corresponding second input buffer of the first voltage signal and the second voltage signal, respectively.

6. The semiconductor device of claim 5 , wherein the clock distortion calibration circuitry is configured to convert the trim value into the one or more biasing voltages and/or biasing currents using biasing circuitry.

7. The semiconductor device of claim 1 , wherein the trim value is a first trim value associated with the first duty cycle of the first voltage signal, and wherein the clock distortion calibration circuitry is further configured to track the first trim value and a second trim value associated with the second duty cycle of the second voltage signal.

8. The semiconductor device of claim 7 , wherein the clock distortion calibration circuitry is further configured to:
compare the first duty cycle to a threshold; and
adjust the first trim value based on the comparison of the first duty cycle to the threshold.

9. The semiconductor device of claim 8 , wherein the clock distortion calibration circuitry is configured to adjust the first trim value to adjust the first duty cycle by an amount dependent on the threshold.

10. The semiconductor device of claim 1 , wherein the clock distortion calibration circuitry is further configured to compare the first duty cycle to a threshold.

11. The semiconductor device of claim 10 , wherein the clock distortion calibration circuitry is further configured to adjust the trim value based on the comparison of the first duty cycle to the threshold.

12. The semiconductor device of claim 1 , wherein the clock distortion calibration circuitry is configured to adjust the trim value to (1) decrease the first duty cycle of the first voltage signal by one half of a difference between the first duty cycle and the second duty cycle of the second voltage signal and (2) increase the second duty cycle of the second voltage signal by one half of the difference.

13. The semiconductor device of claim 1 , further comprising a clock generator configured to produce the clock signal.

14. A method of operating clock distortion calibration circuitry to calibrate a first duty cycle of a first voltage signal of a clock signal and a second duty cycle of a second voltage signal of the clock signal, the method comprising:
measuring the first duty cycle;
measuring the second duty cycle;
comparing the first duty cycle to the second duty cycle;
based on the comparison, adjusting a trim value associated with at least one of the first voltage signal and the second voltage signal to adjust the first trim value and/or the second trim value to the average of the first duty cycle and the second duty cycle;
converting the trim value into one or more biasing voltages and/or biasing currents; and
calibrating at least one of the first duty cycle and the second duty cycle by applying the one or more biasing voltages and/or biasing currents to at least one of a corresponding first input buffer and a corresponding second input buffer of the first voltage signal and the second voltage signal, respectively.

15. The method of claim 14 , wherein measuring the first duty cycle comprises obtaining a first direct current (dc) level representation of the first duty cycle, and wherein measuring the second duty cycle comprises obtaining a second dc level representation of the second duty cycle.

16. The method of claim 15 further comprising converting the first dc level representation into a first digital signal representation of the first duty cycle and converting the second dc level representation into a second digital signal representation of the second duty cycle.

17. The method of claim 14 , wherein
measuring the first duty cycle comprises obtaining a first direct current (dc) level representation of the first duty cycle, and
the method further comprises:
converting the first dc level representation into a first digital signal representation of the first duty cycle;
producing a dc level representation of an acceptable duty cycle;
converting the dc level representation of the acceptable duty cycle into a second digital signal representation of the acceptable duty cycle;
comparing the first digital signal representation to the second digital signal representation; and
based on the comparison of the first digital signal representation to the second digital signal representation, determining whether the first duty cycle is sufficient.

18. The method of claim 17 , wherein the one or more biasing voltages and/or biasing currents are a first set of biasing voltages and/or biasing currents, and wherein the method further comprises:
based on a determination that the first duty cycle is not sufficient, adjusting the trim value;
converting the trim value into a second set of biasing voltages and/or biasing currents; and
calibrating the first duty cycle by a predetermined value by applying at least one biasing voltage and/or biasing current in the second set of biasing voltages and/or biasing currents to the corresponding first input buffer of the first voltage signal.

19. The method of claim 18 , wherein the trim value is a first trim value associated with the first duty cycle of the first voltage signal, and wherein the method further comprises tracking the first trim value and a second trim value associated with the second duty cycle of the second voltage signal.

20. A system, comprising:
a host device; and
a plurality of semiconductor dies operably connected to the host device, wherein

Assignees

• Micron Technology Inc

Inventors

• Wang Guan
• Tang Qiang
• Ghalam Ali Feiz Zarrin

Classifications

• H03K5/1565 Primary

  the output pulses having a constant duty cycle · CPC title

• H04L25/063

  Setting decision thresholds using feedback techniques only · CPC title

• G11C29/023

  in clock generator or timing circuitry · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G06F1/10 Primary

  Distribution of clock signals {, e.g. skew} · CPC title