Look ahead normaliser

Patent metadata

Field	Value
Publication number	US-11768658-B2
Application number	US-202217875747-A
Country	US
Kind code	B2
Filing date	Jul 28, 2022
Priority date	Feb 28, 2020
Publication date	Sep 26, 2023
Grant date	Sep 26, 2023

Abstract

Apparatus includes hardware logic arranged to normalise an n-bit input number. The hardware logic comprises at least a first hardware logic stage, an intermediate hardware logic stage and a final hardware logic stage. Each stage comprises a left shifting logic element, the first and intermediate stages each also comprise a plurality of OR-reduction logic elements and the intermediate and final stages each also comprise one or more multiplexers. The OR-reduction logic elements operate on different subsets of bits from the number input to the particular stage. In the intermediate and final hardware logic stages, a first of the multiplexers selects an OR-reduction result received from a previous hardware logic stage and the left shifting logic element is arranged to perform left shifting on the updated binary number received from an immediately previous hardware logic stage dependent upon the selected OR-reduction result.

First claim

What is claimed is:

1. An apparatus comprising hardware logic, the hardware logic comprising:
a first hardware logic stage comprising a plurality of OR-reduction logic elements and arranged to output a first updated binary number, wherein each OR-reduction logic element is arranged to perform OR-reduction on a different subset of bits from an input number, the first updated binary number comprising a shifted version of the input number, the shifting dependent upon a value output by a first of the OR-reduction elements;
one or more intermediate hardware logic stages, each arranged to output an intermediate updated binary number and comprising a plurality of OR-reduction logic elements and one or more multiplexers, wherein each OR-reduction logic element in an intermediate stage is arranged to perform OR-reduction on a different subset of bits from an updated binary number received from an immediately previous hardware logic stage and a first of the multiplexers is arranged to select one of a plurality of OR-reduction results received from a previous hardware logic stage, the intermediate updated binary number comprising a shifted version of the updated binary number received from an immediately previous hardware logic stage, the shifting dependent upon the selected OR-reduction result; and
a final hardware logic stage, comprising one or more multiplexers and arranged to output a final updated binary number, wherein a first of the multiplexers is arranged to select one of a plurality of OR-reduction results received from a previous hardware logic stage, the final updated binary number comprising a shifted version of the updated binary number received from an immediately previous hardware logic stage, the shifting dependent upon the selected OR-reduction result.

2. The apparatus according to claim 1 , wherein the final hardware stages does not comprise any OR-reduction logic elements.

3. The apparatus according to claim 1 , wherein each stage is further arranged to invert the OR-reduction result selected by the first multiplexer in the stage and output the inverted result as a next most significant bit of a leading zero count value, wherein the first hardware logic stage is arranged to output the most significant bit of the leading zero count value.

4. The apparatus according to claim 1 , wherein:
the first hardware logic stage is arranged to shift the input number by k 1 bits or zero bits dependent upon the value output by the first of the OR-reduction logic elements in the first stage, and wherein k 1 is a number of bits reduced by the first of the OR-reduction logic elements in the first stage; and
an i th hardware logic stage is arranged to shift the input number by k i bits or zero bits dependent upon the OR-reduction result selected by the multiplexer in the i th stage, and wherein k i is a number of bits reduced by the OR-reduction logic element that generated the selected OR-reduction result and wherein the i th stage is an intermediate hardware logic stage or the final hardware logic stage.

5. The apparatus according to claim 1 , wherein:
the first hardware logic stage comprises three OR-reduction logic elements, the first of the OR-reduction logic elements being arranged to perform OR-reduction on bits in a first and second of four portions of the input number, a second of the OR-reduction logic elements being arranged to perform OR-reduction on bits in the first portion of the input number and a third of the OR-reduction logic elements being arranged to perform OR-reduction on bits in the third portion of the input number;
each intermediate hardware logic stage comprises two OR-reduction logic elements, a first of the OR-reduction logic elements in an intermediate hardware logic stage being arranged to perform OR-reduction on bits in a first of 2 i+1 portions of the updated binary number received from the immediately previous hardware logic stage and a second of the OR-reduction logic elements in an intermediate hardware logic stage being arranged to perform OR-reduction on a third portion of the updated binary number received from the immediately previous hardware logic stage, wherein i is a number of the stage in the apparatus such that for the first hardware stage i=1 and for a first intermediate stage, i=2; and
wherein the multiplexer in an intermediate hardware logic stage or the final hardware logic stage is arranged to select one of a plurality of OR-reduction results received from an immediately previous hardware logic stage.

6. The apparatus according to claim 5 , wherein each of the 2 i+1 portions of an updated binary number input to an i th stage comprise an identical number of bits.

7. The apparatus according to claim 5 , wherein for an i th hardware logic stage, the first portion of the updated binary number input to that stage comprises bits:

n
-

1
:
n

-

n

2

i
+
1

and the third portion of the updated binary number input to that stage comprises bits:

n
-

n

2
i

-

1
:
n

-

3
⁢
n

2

i
+
1

.

8. The apparatus according to claim 1 , wherein:
the first hardware logic stage comprises seven OR-reduction logic elements, the first of the OR-reduction logic elements being arranged to perform OR-reduction on bits in a first four of eight portions of the input number, a second of the OR-reduction logic elements being arranged to perform OR-reduction on bits in a first two portions of the input number, a third of the OR-reduction logic elements being arranged to perform OR-reduction on fifth and sixth portions of the input number, a fourth of the OR-reduction logic elements being arranged to perform OR-reduction on a first portion of the input number, a fifth of the OR-reduction logic elements being arranged to perform OR-reduction on a third portion of the input number, a sixth of the OR-reduction logic elements being arranged to perform OR-reduction on a fifth portion of the input number and a seventh of the OR-reduction logic elements being arranged to perform OR-reduction on a seventh portion of the input number;
each intermediate hardware logic stage comprises four OR-reduction logic elements, wherein each of the OR-reduction logic elements in an intermediate hardware logic stage is arranged to perform OR-reduction on bits in a first, third, fifth and seventh of 2 i+2 portions of an updated binary number input to the stage respectively, where i is a number of the stage and for a first intermediate stage, i=2;
a first multiplexer in a first intermediate hardware logic stage is arranged to select one of two OR-reduction results received from the first hardware logic stage, the first of the two O

Assignees

• Imagination Tech Ltd

Inventors

• Van Benthem Casper

Classifications

• G06F5/01 Primary

  for shifting, e.g. justifying, scaling, normalising {(digital stores in which the information is moved stepwise, e.g. shift-registers G11C19/00; digital stores in which the information circulates G11C21/00)} · CPC title

• G06F7/49936 Primary

  Normalisation mentioned as feature only · CPC title

• G06F9/30025 Primary

  Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion · CPC title

• G06F5/012

  in floating-point computations · CPC title

• G06F7/499

  Denomination or exception handling, e.g. rounding or overflow · CPC title