Partially and fully parallel normaliser

Patent metadata

Field	Value
Publication number	US-10223068-B2
Application number	US-201715636100-A
Country	US
Kind code	B2
Filing date	Jun 28, 2017
Priority date	Dec 20, 2013
Publication date	Mar 5, 2019
Grant date	Mar 5, 2019

Abstract

Hardware logic arranged to normalize (or renormalize) an n-bit input number is described in which at least a proportion of a left shifting operation is performed in parallel with a leading zero count operation. In various embodiments the left shifting and the leading zero count are performed independently. In various other embodiments, a subset of the bits output by a leading zero counter are input to a left shifter and the output from the left shifter is input to a renormalization block which completes the remainder of the left shifting operation independently of any further input from the leading zero counter.

First claim

What is claimed is:

1. Hardware logic arranged to normalize an input binary number, the hardware logic comprising:
a zero counter arranged to compute a number of leading or trailing zeros in the binary number; and
normalization logic arranged to perform normalization of the binary number, the normalization comprising at least one shifting operation;
wherein at least a portion of the normalization is performed in parallel with the computing of the number of leading or trailing zeros.

2. Hardware logic according to claim 1 , wherein said at least a portion of the normalization is performed in parallel with the computing of the number of leading or trailing zeros and without input from the zero counter.

3. Hardware logic according to claim 1 , wherein the normalization logic comprises a normalizer block arranged to operate independently of the zero counter.

4. Hardware logic according to claim 3 , wherein the normalizer block comprises hardware logic arranged to combine pairs of bits in the binary number according to:
r i j:j =α j .α j−n+1+i

where:
. represents an AND logic function,
n is a number of bits in the binary number,
j is a bit index associated with each of the n-bits in the binary number,
α j is the j th bit in the binary number, and
i is a bit index associated with each bit r i output by the normalizer block.

5. Hardware logic according to claim 4 , wherein the normalizer block further comprises hardware logic arranged to combine values r i j:j in the form of a tree of logic elements to compute output bits r i n−1:0 based on at least one of:
r i j:k =r i j:t +B j:t r i t−1:k and
r i j:k =( r i j:t +B j:t )( r i j:t +r i t−1:k )
where:
+ represents an OR logic function,
t and k are natural numbers, and
B j:t = α j . α j−1 . . . α t+1 . α t .

6. Hardware logic according to claim 1 , wherein the normalization logic comprises:
a shifter arranged to receive a subset of the bits, starting from a most significant bit, generated by the zero counter and to shift the binary number based on the received bits; and
a normalizer block arranged to receive an output from the shifter and to generate an output comprising a normalized version of the binary number.

7. Hardware logic according to claim 6 , wherein the normalizer block comprises hardware logic arranged to combine pairs of input bits according to:
r i j:j =α′ j .α′ j−n+1+i

where:
. represents an AND logic function,
n is a number of bits in the binary number,
j is a bit index associated with each of the n-bits in the binary number,
α′ j is the j th bit in the number output by the shifter, and
i is a bit index associated with each bit r i output by the normalizer block.

8. Hardware logic according to claim 7 , wherein the normalizer block further comprises hardware logic arranged to combine values r i j:j in the form of a tree of logic elements to compute output bits r i n−1:n+1−2 α−h based on at least one of:
r i j:k =r i j:t +B j:t r i t−1:k and
r i j:k =( r i j:t +B j:t )( r i j:t +r i t−1:k )
where:
+ represents an OR logic function,
t and k are natural numbers,
α=└ log 2 n ┘+1,

the subset of bits received from the zero counter comprises h bits, and
B j:t = α j . α j−1 . . . α t+1 . α t .

9. A method of normalizing an input binary number, the method comprising:
computing, by hardware logic a number of leading or trailing zeros in the binary number in a zero counter; and
normalizing the binary number in normalization logic, the normalization comprising at least one shifting operation and wherein at least a portion of the normalization is performed in parallel with the computing of the number of leading or trailing zeros.

10. The method as set forth in claim 9 , wherein at least a portion of the normalization operation is performed in parallel with the computing of the number of leading or trailing zeros and without input from the number of leading or trailing zeros computation.

11. A non-transitory computer readable storage medium having stored thereon computer executable program code that when executed causes at least one processor to:
compute a number of leading or trailing zeros in a binary number in a zero counter; and
normalize the binary number, the normalization comprising at least one shifting operation, wherein at least a portion of the normalization is performed in parallel with the computing of the number of leading or trailing zeros.

12. The non-transitory computer readable storage medium as set forth in claim 11 , wherein at least a portion of the normalization operation is performed in parallel with the computing of the number of leading or trailing zeros and without input from the number of leading or trailing zeros computation.

13. A non-transitory computer readable storage medium having stored thereon computer executable program code that, when executed at a computer system for generating a representation of a digital circuit from definitions of circuit elements and data defining rules for combining those circuit elements, cause the computer system to generate hardware logic arranged to normalize an input binary number, the hardware logic comprising:
a zero counter arranged to compute a number of leading or trailing zeros in the binary number; and
normalization logic arranged to perform normalization of the binary number, the normalization comprising at least one shifting operation,
wherein at least a portion of the normalization is performed in parallel with the computing of the number of leading or trailing zeros.

14. The non-transitory computer readable storage medium as set forth in claim 13 , wherein at least a portion of the normalization operation is performed in parallel with the computing of the number of leading or trailing zeros and without input from the number of leading or trailing zeros computation.

Assignees

• Imagination Tech Ltd

Inventors

• Drane Theo Alan

Classifications

• G06F2205/003

  Reformatting, i.e. changing the format of data representation · CPC title

• G06F5/01 Primary

  for shifting, e.g. justifying, scaling, normalising {(digital stores in which the information is moved stepwise, e.g. shift-registers G11C19/00; digital stores in which the information circulates G11C21/00)} · CPC title

• G06F7/74

  Selecting or encoding within a word the position of one or more bits having a specified value, e.g. most or least significant one or zero detection, priority encoders {(with shifting G06F5/01)} · CPC title