Multi-layer crystalline back gated thin film transistor

Patent metadata

Field	Value
Publication number	US-11764306-B2
Application number	US-202117472879-A
Country	US
Kind code	B2
Filing date	Sep 13, 2021
Priority date	Sep 29, 2017
Publication date	Sep 19, 2023
Grant date	Sep 19, 2023

Abstract

Described is an apparatus which comprises: a gate comprising a metal; a first layer adjacent to the gate, the first layer comprising a dielectric material; a second layer adjacent to the first layer, the second layer comprising a second material; a third layer adjacent to the second layer, the third layer comprising a third material including an amorphous metal oxide; a fourth layer adjacent to the third layer, the fourth layer comprising a fourth material, wherein the fourth and second materials are different than the third material; a source partially adjacent to the fourth layer; and a drain partially adjacent to the fourth layer.

First claim

We claim:

1. An integrated circuit comprising:
a gate comprising a metal;
a first layer adjacent to the gate, the first layer comprising a dielectric material;
a second layer adjacent to the first layer, the second layer comprising a second material;
a third layer adjacent to the second layer, the third layer comprising a third material including an amorphous metal oxide;
a fourth layer adjacent to the third layer, the fourth layer comprising a fourth material that is crystalline, wherein the second and fourth materials are different than the third material;
a source at least partially adjacent to the fourth layer; and
a drain at least partially adjacent to the fourth layer;
wherein the gate, the first layer, the second layer, the third layer, the fourth layer, the source, and the drain are positioned in one or more interconnect layers.

2. The integrated circuit of claim 1 , wherein the second material is crystalline.

3. The integrated circuit of claim 1 , comprising a capacitor, coupled to one of the source or the drain.

4. The integrated circuit of claim 1 , wherein the one or more interconnect layers are above a device layer.

5. The integrated circuit of claim 1 , wherein the dielectric material is a first dielectric material and includes a high-K dielectric material, and wherein the one or more interconnect layers comprise conductive interconnects embedded in a second dielectric material.

6. The integrated circuit of claim 1 , wherein the source and the drain comprise a material which includes one or more of: titanium, nitrogen, tungsten, carbon, platinum, chromium, hafnium, or tantalum.

7. The integrated circuit of claim 1 , wherein the dielectric material is a high-K dielectric material, which includes one or more of: hafnium silicate, zirconium silicate, hafnium dioxide, zirconium dioxide, aluminum oxide, or nitride hafnium silicate.

8. The integrated circuit of claim 1 , wherein the dielectric material is a high-K dielectric material which includes one or more of hafnium, silicon, oxygen, zirconium, aluminum, and nitrogen.

9. The integrated circuit of claim 1 , wherein the second or fourth materials include one or more of: c axis aligned crystalline indium gallium zinc oxide (IGZO), crystalline IGZO, yttrium-doped zinc oxide (YZO), zinc oxide (ZnO), indium zinc oxide (IZO), zinc tin oxide (ZTO), low temperature poly silicon (Si), low temperature poly germanium (Ge), or one or more transmission metal di-chalcogenides (TMDs).

10. The apparatus of claim 9 , wherein the one or more TMDs include one or more of: molybdenum disulfide, tungsten disulfide, molybdenum diselenide, tungsten diselenide, or molybdenum ditelluride.

11. The apparatus of claim 1 , wherein the second or fourth materials include one or more of: indium, gallium, zinc, oxygen, yttrium, tin, germanium, silicon, molybdenum, selenium, tungsten, sulfur, or tellurium.

12. The apparatus of claim 1 , wherein the amorphous metal oxide of the third layer includes indium gallium zinc oxide (IGZO).

13. The apparatus of claim 1 , wherein the second, third, and fourth layers have a combined thickness of less than 60 nm.

14. The apparatus of claim 1 , wherein each of the source, the drain, and the metal of the gate comprise a material which includes one or more of: titanium, nitrogen, tungsten, carbon, platinum, chromium, hafnium, or tantalum.

15. An apparatus comprising:
a thin film transistor (TFT) including:
a gate comprising a metal;
a first layer adjacent to the gate, the first layer comprising a dielectric material;
a second layer adjacent to the first layer, the second layer comprising a second material;
a third layer adjacent to the second layer, the third layer comprising a third material including an amorphous metal oxide;
a fourth layer adjacent to the third layer, the fourth layer comprising a fourth material, wherein the second and fourth materials are different than the third material;
a source partially adjacent to the fourth layer; and
a drain partially adjacent to the fourth layer;

a capacitor coupled the TFT;
a word-line coupled to the gate of the TFT; and
a bit-line coupled to one or more of the source and the drain of the TFT, wherein the TFT and the capacitor are positioned in one or more interconnect layers.

16. The apparatus of claim 15 , comprising one or more circuitries positioned in a front-end-of-line (FEOL) of the die, wherein the one or more circuitries are coupled to at least one of the bit-line and word-line.

17. The apparatus of claim 15 , wherein the second and fourth materials are crystalline.

18. A system comprising:
a processor circuitry to execute one or more instructions;
a memory coupled to the processor circuitry, the memory including:
a gate comprising a metal;
a first layer adjacent to the gate, the first layer comprising a dielectric material;
a second layer adjacent to the first layer, the second layer comprising a second material;
a third layer adjacent to the second layer, the third layer comprising a third material including an amorphous metal oxide;
a fourth layer adjacent to the third layer, the fourth layer comprising a fourth material, wherein the second and fourth materials are different than the third material;
a source partially adjacent to the fourth layer; and
a drain partially adjacent to the fourth layer;
wherein the gate, the first layer, the second layer, the third layer, the fourth layer, the source, and the drain are positioned in one or more interconnect layers.

19. The system of claim 18 , wherein the second and fourth materials are crystalline.

20. The system of claim 18 , wherein the source and the drain are coplanar, and the gate, the first layer, the second layer, the third layer, and the fourth layer are not coplanar.

Assignees

• Intel Corp

Inventors

• Le Van H
• Sharma Abhishek A
• Dewey Gilbert
• Millard Kent
• Kavalieros Jack
• Shivaraman Shriram
• Tronic Tristan A
• Gardner Sanaz
• Weber Justin R
• Ghani Tahir
• Tan Li Huey
• Lin Kevin

Classifications

• H10D62/82

  Heterojunctions · CPC title

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D87/00

  Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate · CPC title

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title