Semiconductor device, inverter circuit, drive device, vehicle, and elevator

Patent metadata

Field	Value
Publication number	US-11764276-B2
Application number	US-202117447003-A
Country	US
Kind code	B2
Filing date	Sep 7, 2021
Priority date	Dec 11, 2020
Publication date	Sep 19, 2023
Grant date	Sep 19, 2023

Abstract

A semiconductor device according to an embodiment includes: a silicon carbide layer having a first plane parallel to a first direction and a second direction orthogonal to the first direction, and a second plane facing the first plane, the silicon carbide layer including a first trench and a second trench extending in the first direction; a gate electrode in the first trench and the second trench; a gate insulating layer; a gate wiring extending in the second direction, intersecting with the first trench and the second trench, connected to the gate electrode; a first electrode; a second electrode; and an interlayer insulating layer provided between the gate electrode and the first electrode. Neither the gate electrode nor the gate wiring is present between an end of the first trench in the first direction and the interlayer insulating layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a silicon carbide layer having a first plane parallel to a first direction and a second direction orthogonal to the first direction, and a second plane facing the first plane, the silicon carbide layer including a first trench provided on a side of the first plane and extending in the first direction, a second trench provided on the side of the first plane, the second trench extending in the first direction, and the second trench separated from the first trench in the second direction, an n-type first silicon carbide region, a p-type second silicon carbide region provided between the first silicon carbide region and the first plane and provided between the first trench and the second trench, and an n-type third silicon carbide region provided between the second silicon carbide region and the first plane and provided between the first trench and the second trench;
a gate electrode provided in the first trench and the second trench;
a gate insulating layer provided between the gate electrode and the silicon carbide layer;
a gate wiring extending in the second direction, the gate wiring intersecting with the first trench and the second trench, the gate wiring connected to the gate electrode, and the gate wiring made of a same material as the gate electrode;
a first electrode provided on the side of the first plane of the silicon carbide layer and electrically connected to the third silicon carbide region;
a second electrode provided on a side of the second plane of the silicon carbide layer; and
an interlayer insulating layer provided between the gate electrode and the first electrode, wherein
neither the gate electrode nor the gate wiring is present between an end of the first trench in the first direction and the interlayer insulating layer.

2. The semiconductor device according to claim 1 , wherein
the gate electrode and the gate wiring are made of polycrystalline silicon.

3. The semiconductor device according to claim 1 , wherein
the gate insulating layer is provided between the first plane between the first trench and the second trench and the gate wiring, and the gate wiring is in contact with the gate insulating layer.

4. The semiconductor device according to claim 1 , further comprising:
a metal wiring extending in the second direction, the metal wiring intersecting with the first trench and the second trench, the interlayer insulating layer being provided between the gate wiring and the metal wiring, and the metal wiring being electrically connected to the gate wiring.

5. The semiconductor device according to claim 4 , wherein
the metal wiring is in contact with the gate wiring.

6. The semiconductor device according to claim 4 , wherein
the metal wiring and the first electrode are made of a same material.

7. The semiconductor device according to claim 1 , wherein
the silicon carbide layer further includes
a third trench provided on the side of the first plane, the third trench extending in the first direction, and the third trench provided between the first trench and the second trench;
a fourth trench provided on the side of the first plane, the fourth trench extending in the second direction, and the fourth trench separated from the first trench and the second trench in the first direction;
a fifth trench provided on the side of the first plane, the fifth trench extending in the first direction, the fifth trench provided between the first trench and the second trench, the fifth trench provided between the third trench and the fourth trench, and the fifth trench intersecting with the gate wiring; and
a p-type fourth silicon carbide region provided between the third trench and the first silicon carbide region,
a part of the first electrode is provided in the third trench, and the first electrode is electrically connected to the fourth silicon carbide region, and
the gate electrode is further provided in the fifth trench.

8. The semiconductor device according to claim 7 , wherein
the fourth silicon carbide region is provided between the fourth trench and the first silicon carbide region and between the fifth trench and the first silicon carbide region.

9. The semiconductor device according to claim 7 , wherein
the third trench, the fourth trench, and the fifth trench are continuous.

10. The semiconductor device according to claim 7 , wherein
the third trench and the fifth trench are separated from each other.

11. The semiconductor device according to claim 10 , wherein
the fourth trench and the fifth trench are separated from each other.

12. The semiconductor device according to claim 7 , wherein
the gate electrode is further provided in the fourth trench.

13. The semiconductor device according to claim 1 , wherein
the first direction is a direction inclined by 0° or more and 8° or less with respect to a <11-20> direction.

14. An inverter circuit comprising the semiconductor device according to claim 1 .

15. A drive device comprising the semiconductor device according to claim 1 .

16. A vehicle comprising the semiconductor device according to claim 1 .

17. An elevator comprising the semiconductor device according to claim 1 .

Assignees

• Toshiba Kk

Inventors

• Kimoto Shinichi
• Iijima Ryosuke
• Harada Shinsuke

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10D64/2527

  for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies · CPC title

• H10D30/0297

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title

• H10D30/0295

  using recessing of the source electrodes · CPC title

• H10D64/661

  the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation (having lateral variation in the gate structure H10D64/671) · CPC title