Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10475916-B2
Application number	US-201815938176-A
Country	US
Kind code	B2
Filing date	Mar 28, 2018
Priority date	Mar 30, 2017
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

A semiconductor device in which a trench in a cell outer peripheral region configured to pull out a gate electrode and a trench in a cell region having a vertical transistor are formed with the same width to enable a reduction in chip area, and a manufacturing method thereof in which a gate contact hole is formed directly on a trench in a cell outer peripheral region on a self-alignment basis, and a gate wiring electrode is connected thereto are provided.

First claim

What is claimed is:

1. A semiconductor device comprising:
a cell region on a substrate and including a vertical transistor having a first trench;
a cell outer peripheral region having a second trench connected to the first trench;
a gate insulating film on a bottom surface and a side surface of the first trench and on a bottom surface and a side surface of the second trench up to a first height; and
a gate electrode embedded up to the first height inside each of the first and second trenches along the gate insulating film,
the cell outer peripheral region configured to pull out a potential of the gate electrode, and having:
a sidewall insulation region contacting the side surface of the second trench from the first height to an upper surface of the substrate, the first height lower than the upper surface of the substrate and higher than the bottom surface of the second trench; and
a gate metal wiring having a lower portion surrounded by and in contact with the sidewall insulation region and contacting an entire upper surface of the gate electrode, the gate metal wiring in a region above the first height inside the second trench.

2. The semiconductor device according to claim 1 , wherein a width of the first trench and a width of the second trench are substantially the same.

3. The semiconductor device according to claim 2 , wherein a second insulating film having an upper portion at a position higher than an upper end of the first trench is on the gate electrode in the first trench.

4. The semiconductor device according to claim 1 , wherein the sidewall insulation region comprising a first insulating film along an inside portion of the side surface of the second trench.

5. The semiconductor device according to claim 4 , wherein a second insulating film having an upper portion at a position higher than an upper end of the first trench is on the gate electrode in the first trench.

6. The semiconductor device according to claim 1 , wherein a second insulating film having an upper portion at a position higher than an upper end of the first trench is on the gate electrode in the first trench.

7. A semiconductor device comprising:
a cell region on a substrate and including a vertical transistor having a first trench;
a cell outer peripheral region having a second trench connected to the first trench;
a gate insulating film on a bottom surface and a side surface of the first trench and on a bottom surface and a side surface of the second trench up to a first height; and
a gate electrode embedded up to the first height inside each of the first and second trenches along the gate insulating film,
the cell outer peripheral region configured to pull out a potential of the gate electrode, and having:
a sidewall insulation region along the side surface of the second trench from the first height lower than a surface of the substrate and higher than the bottom surface of the second trench to a second height of the surface of the substrate; and
a gate metal wiring having a lower portion contacting the gate electrode and in a region above from the first height inside the second trench, surrounded by the sidewall insulation region
wherein the sidewall insulation region comprises an impurity diffusion region in the substrate along an outside portion of the side surface of the second trench.

8. The semiconductor device according to claim 7 , wherein a second insulating film having an upper portion at a position higher than an upper end of the first trench is on the gate electrode in the first trench.

9. A semiconductor device comprising:
a substrate;
a cell region on the substrate and including a vertical transistor having a first trench; and
a cell outer peripheral region having a second trench connected to the first trench,
each of the first trench and the second trench having:
a gate insulating film on a bottom surface and a side surface thereof, and
a gate electrode embedded in the first trench and the second trench respectively along the gate insulating film,
the cell outer peripheral region having:
a sidewall insulation region along and in contact with one of an inside surface or an outside surface of the second trench at least from an upper end of the gate electrode to an uppermost surface of the substrate, and
a gate metal wiring in a region surrounded by and in contact with an entire upper end of the gate electrode in the second trench and the sidewall insulation region.

10. The semiconductor device according to claim 9 , wherein a width of the first trench and a width of the second trench are substantially the same.

11. The semiconductor device according to claim 10 , wherein a second insulating film having an upper portion at a position higher than an upper end of the first trench is on the gate electrode in the first trench.

12. The semiconductor device according to claim 9 , wherein the sidewall insulation region comprises a first insulating film along an inside portion of the side surface of the second trench.

13. The semiconductor device according to claim 12 , wherein a second insulating film having an upper portion at a position higher than an upper end of the first trench is on the gate electrode in the first trench.

14. The semiconductor device according to claim 9 , wherein a second insulating film having an upper portion at a position higher than an upper end of the first trench is on the gate electrode in the first trench.

15. The semiconductor device according to claim 9 , wherein a second insulating film having an upper portion at a position higher than an upper end of the first trench is on the gate electrode in the first trench.

16. A semiconductor device comprising:
a substrate;
a cell region on the substrate and including a vertical transistor having a first trench; and
a cell outer peripheral region having a second trench connected to the first trench,
each of the first trench and the second trench having:
a gate insulating film on a bottom surface and a side surface thereof, and
a gate electrode embedded in the first trench and the second trench respectively along the gate insulating film,
the cell outer peripheral region having:
a sidewall insulation region along one of an inside surface or an outside surface of the second trench at least from an upper end of the gate electrode to an uppermost surface of the substrate, and
a gate metal wiring in a region surrounded by an upper end of the gate electrode in the second trench and the sidewall insulation region
wherein the sidewall insulation region comprises an impurity diffusion region in the substrate along an outside portion of the side surface of the second trench.

17. The semiconductor device according to claim 16 , wherein a second insulating film having an upper portion at a position higher than an upper end of the first trench is on the gate electrode in the first trench.

Assignees

• Ablic Inc

Inventors

• Hatakenaka Masahiro
• Yoshimura Mitsuhiro

Classifications

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L23/5226

  Electricity · mapped topic

• H01L29/7813 Primary

  Electricity · mapped topic