Display panel and display device for adjusting impedance

Patent metadata

Field	Value
Publication number	US-11763772-B2
Application number	US-202117621700-A
Country	US
Kind code	B2
Filing date	Jan 28, 2021
Priority date	Dec 18, 2020
Publication date	Sep 19, 2023
Grant date	Sep 19, 2023

Abstract

Provided are a display panel and a display device. The display panel includes a gate drive circuit, a plurality of impedance regulation circuits and a control module. The gate drive circuit includes a plurality of cascaded first shift registers. The plurality of cascaded first shift registers are electrically connected to a plurality of scanning lines in one to one correspondence; and the plurality of impedance regulation circuits are in one-to-one correspondence with the plurality of scanning lines. Each of the plurality of impedance regulation circuits is in series connection between a first shift register corresponding to the each of the plurality of impedance regulation circuits and a scanning line corresponding to the each of the plurality of impedance regulation circuits. The each of the plurality of impedance regulation circuits includes at least one transistor.

First claim

What is claimed is:

1. A display panel for adjusting impedance, comprising:
a gate drive circuit comprising a plurality of cascaded first shift registers, wherein the plurality of cascaded first shift registers are electrically connected to a plurality of scanning lines in one to one correspondence and each stage of the plurality of cascaded first shift registers is configured to provide a scanning pulse signal to a scanning line correspondingly connected;
a plurality of impedance regulation circuits in one-to-one correspondence with the plurality of scanning lines, wherein each of the plurality of impedance regulation circuits is in series connection between a first shift register corresponding to the each of the plurality of impedance regulation circuits and a scanning line corresponding to the each of the plurality of impedance regulation circuits; and the each of the plurality of impedance regulation circuits comprises at least one transistor; and
a control module electrically connected to the plurality of impedance regulation circuits and configured to adjust an impedance of the at least one transistor in the each of the plurality of impedance regulation circuits.

2. The display panel for adjusting impedance according to claim 1 , wherein the control module is configured to control turn-on and turn-off of the at least one transistor in the each of the plurality of impedance regulation circuits to adjust the impedance of the at least one transistor in the each of the plurality of impedance regulation circuits.

3. The display panel for adjusting impedance according to claim 1 , wherein the control module is configured to adjust a gate voltage value of the at least one transistor in the each of the plurality of impedance regulation circuits to adjust the impedance of the at least one transistor in the each of the plurality of impedance regulation circuits.

4. The display panel for adjusting impedance according to claim 1 , wherein the each of the plurality of impedance regulation circuits comprises a first impedance regulation subcircuit, and the first impedance regulation subcircuit comprises N transistors connected in series; and a gate of an i-th transistor of the N transistors in the first impedance regulation subcircuit of the each of the plurality of impedance regulation circuits is electrically connected to a same output terminal of the control module,
wherein N is a positive integer greater than 1, and i is a positive integer less than or equal to N.

5. The display panel for adjusting impedance according to claim 4 , wherein the control module comprises N cascaded first shift latch modules; and each stage of first shift latch module of the N cascaded first shift latch modules receives and latches a shift signal output from a previous-stage first shift latch module of the N cascaded first shift latch modules; and
the gate of the i-th transistor of the N transistors in the first impedance regulation subcircuit of the each of the plurality of impedance regulation circuits is electrically connected to an i-th-stage first shift latch module of the N cascaded first shift latch modules.

6. The display panel for adjusting impedance according to claim 5 , wherein a first-stage first shift latch module of the N cascaded first shift latch modules comprises a first enable signal terminal; a k-th-stage first shift latch module of the N cascaded first shift latch modules comprises a first shift signal enable terminal; the each stage of first shift latch module of the N cascaded first shift latch modules comprises a first clock signal terminal and an output terminal; and the control module is configured to control an impedance of the each of the plurality of impedance regulation circuits according to an input signal of the first enable signal terminal and an input signal of the first clock signal terminal of the each stage of first shift latch module, and the first shift signal enable terminal of the k-th-stage first shift latch module of the N cascaded first shift latch modules is connected to an output terminal of a (k−1)-th-stage first shift latch module of the N cascaded first shift latch modules, wherein K is a positive integer greater than 1 and less than or equal to N.

7. The display panel for adjusting impedance according to claim 4 , wherein off-impedances of at least part of the N transistors in the first impedance regulation subcircuit of the each of the plurality of impedance regulation circuits are different.

8. The display panel for adjusting impedance according to claim 7 , wherein off-impedances of the N transistors in the first impedance regulation subcircuit of the each of the plurality of impedance regulation circuits are in a geometric sequence.

9. The display panel for adjusting impedance according to claim 1 , wherein the each of the plurality of impedance regulation circuits comprises a second impedance regulation subcircuit, and the second impedance regulation subcircuit comprises M transistors connected in parallel; and a gate of a j-th transistor of the M transistors in the second impedance regulation subcircuit of the each of the plurality of impedance regulation circuits is electrically connected to a same output terminal of the control module,
wherein M is a positive integer greater than 1, and j is a positive integer less than or equal to M.

10. The display panel for adjusting impedance according to claim 9 , wherein the control module comprises M cascaded second shift latch modules; and each stage of second shift latch module of the M cascaded second shift latch modules receives and latches a shift signal output from a previous-stage second shift latch module of the M cascaded second shift latch modules; and
the gate of the j-th transistor of the M transistors in the second impedance regulation subcircuit of the each of the plurality of impedance regulation circuits is electrically connected to a j-th-stage second shift latch module of the M cascaded second shift latch modules.

11. The display panel for adjusting impedance according to claim 10 , wherein a first-stage second shift latch module of the M cascaded second shift latch modules comprises a second enable signal terminal; an x-th-stage second shift latch module of the M cascaded second shift latch modules comprises a second shift signal enable terminal; the each stage of second shift latch module of the M cascaded second shift latch modules comprises a second clock signal terminal and an output terminal; and the control module is configured to control impedance of the each of the plurality of impedance regulation circuits according to an input signal of the second enable signal terminal and an input signal of the second clock signal terminal of the each stage of second shift latch module, and the second shift signal enable terminal of the x-th-stage second shift latch module is connected to an output terminal of an (x−1)-th-stage second shift latch module of the M cascaded second shift latch modules, wherein x is a positive integer greater than 1 and less than or equal to M.

12. The display panel for adjusting impedance according to claim 9 , wherein on-impedances of the M transistors in the second impedance regulation subcircuit of the each of the plurality of impedance regulation circuits are the same.

13. The display panel for adjusting impedance according to claim 1 , further comprising a driver chip, and the control module is integrated in the driver chip.

14. The display panel for adjusting impedance according to claim 1 , further comprising a display region and a non-display region surrounding the display region, and the control module is located in the non-

Assignees

• Xiamen Tianma Micro Electronics Co Ltd

Inventors

• Zou Zongjun
• Sun Ying
• Xu Yumin

Classifications

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G5/006 Primary

  Details of the interface to the display terminal (specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04) · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2330/06

  Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation · CPC title