Wake-up control circuit for power-gated integrated circuits

Patent metadata

Field	Value
Publication number	US-10620676-B1
Application number	US-201816157992-A
Country	US
Kind code	B1
Filing date	Oct 11, 2018
Priority date	Oct 11, 2018
Publication date	Apr 14, 2020
Grant date	Apr 14, 2020

Abstract

A power gating circuit includes a first transistor to couple a power supply to a gated power rail after receiving a control signal. The power gating circuit also includes two or more transistors coupled in parallel with the first switch, the one or more transistors configured to sequentially couple the power supply to the gated power rail according to a sequence determined by a comparator circuit and one or more cascaded latches.

First claim

The claimed invention is:

1. A power gating circuit, comprising:
a first transistor to couple a power supply to a gated power rail responsive to receiving a control signal;
one or more transistors coupled in parallel with the first transistor, wherein:
the one or more transistors are configured to sequentially couple the power supply to the gated power rail according to a sequence determined by one or more cascaded latches, and
at least one latch of the one or more cascaded latches is configured to receive a signal to determine an interval at which the one or more transistors sequentially couple the power supply to the gated power rail; and

a comparator circuit configured to initiate the sequential coupling responsive to the gated power rail exceeding a threshold voltage.

2. The power gating circuit of claim 1 , wherein at least one transistor of the one or more transistors has a lower on impedance than the first transistor.

3. The power gating circuit of claim 1 , wherein the comparator circuit has an input coupled to the gated power rail and an output coupled a first latch of the one or more cascaded latches.

4. The power gating circuit of claim 1 , wherein the comparator circuit comprises a voltage controlled current source serially coupled to a resistive element.

5. The power gating circuit of claim 4 , wherein the voltage controlled current source is a field effect transistor and the resistive element is at least one of a diode connected field effect transistor or a resistor.

6. The power gating circuit of claim 1 , further including the one or more cascaded latches.

7. The power gating circuit of claim 1 , further comprising a clock circuit to clock the one or more cascaded latches, the clock circuit configured to receive power from a power source other than the gated power rail.

8. The power gating circuit of claim 1 , wherein sequentially coupling the power supply to the gated power rail according to a sequence determined by the one or more cascaded latches limits a current drawn from the power supply below a threshold current while a voltage of the gated power rail changes towards a voltage of the power supply.

9. The power gating circuit of claim 1 , further comprising a reset circuit configured to indicate, based on at least one transistor of the one or more transistors, that a voltage of the gated power rail is higher than a threshold voltage.

10. The power gating circuit of claim 1 , further comprising a linear regulator to provide the power supply.

11. An electronic device having an active mode and a low-power mode, the electronic device comprising:
a gated power rail to power a gated circuit during the active mode; and
a power gating circuit configured to couple a power supply to the gated power rail, the power gating circuit comprising:
a first transistor to couple the power supply to the gated power rail responsive to receiving a control signal, and
one or more transistors to sequentially couple the power supply to the gated power rail at an indicated clock interval according to a sequence determined by one or more synchronously clocked latches; and
a comparator circuit configured to actuate the one or more transistors to sequentially couple the power supply to the gated power rail after the gated power rail transitions to a threshold voltage.

12. The electronic device of claim 11 , further comprising:
a clock circuit coupled to the power supply and to the one or more latches, the clock circuit configured to synchronously clock the one or more latches to sequentially actuate the one or more transistors at an indicated frequency.

13. The electronic device of claim 11 , wherein the comparator circuit comprises:
a sensing transistor to sense a voltage on the gated power rail, and
at least one of a diode connected transistor and a resistor coupled in series with the sensing transistor to generate an output voltage in responsive to the sensed voltage on the gated power rail.

14. The electronic device of claim 13 , wherein the comparator circuit further comprises:
at least one transistor configured to reduce the current consumed by power gating circuit based on the received control signal.

15. The electronic device of claim 11 , wherein the power gating circuit is configured to limit current spikes in the power supply below a threshold value when the electronic device transitions from the low-power mode to the active mode.

16. The electronic device of claim 11 , further comprising a reset circuit configured to indicate, based on at least one transistor of the one or more transistors, whether a voltage of the gated power rail is higher than a threshold voltage.

17. The electronic device of claim 11 , wherein the comparator circuit comprises a voltage controlled current source coupled in series with a resistive element.

18. A method for limiting current spikes in a power supply of an electronic device when the electronic device transitions from a low-power mode to an active mode, the method comprising:
charging a gated power rail by coupling the power supply to the gated power rail using a transistor having at least a specified impedance;
monitoring a voltage of the gated power rail to determine when the gated power rail charges to a threshold voltage level; and
charging the gated power rail towards an active mode voltage of the gated power rail by actuating one or more transistors to sequentially couple the power supply to the gated power rail using one or more cascaded latches, wherein:
the one or more transistors are configured in parallel with the transistor, and
the one or more latches are synchronously clocked to sequentially actuate the one or more transistors at an indicated frequency.

19. The method of claim 18 , wherein at least one of the one or more transistors has a lower impedance than the specified impedance.

Assignees

• Analog Devices Global Unlimited Co

Inventors

• Tejada Jose
• Azcona Cristina

Classifications

• G06F1/26 Primary

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• H03K3/012

  Modifications of generator to improve response time or to decrease power consumption · CPC title

• H03K3/0372 Primary

  of the primary-secondary type · CPC title