Storage device having a controller that communicates with each of two memories through separate interfaces

Patent metadata

Field	Value
Publication number	US-11762558-B2
Application number	US-201916533883-A
Country	US
Kind code	B2
Filing date	Aug 7, 2019
Priority date	Sep 21, 2018
Publication date	Sep 19, 2023
Grant date	Sep 19, 2023

Abstract

A storage device includes a first memory device including a plurality of first memory cells, a second memory device including a plurality of second memory cells having the same type as the plurality of first memory cells, and a controller that communicates with the first memory device through a first memory interface and communicates with the second memory device through a second memory interface having an operating speed higher than an operating speed of the first memory interface.

First claim

What is claimed is:

1. A storage device comprising:
a first controller configured to communicate with an external device through a host interface;
a first memory device including a plurality of first memory cells, and configured to directly communicate with the first controller through a first channel of a first memory interface;
a second memory device including a plurality of second memory cells having a same type as the plurality of first memory cells; and
a second controller configured to directly communicate with the first controller through a second channel of the first memory interface, wherein the second controller directly communicates with the second memory device through a second memory interface, wherein
the first controller communicates first data to the second controller with a program command and, in response to the program command received through the first memory interface, the second controller executes a weighting operation on the first data without programming the first data into the second memory device.

2. The storage device of claim 1 , wherein each of the plurality of first memory cells and the plurality of second memory cells is a NAND flash memory cell.

3. The storage device of claim 1 , wherein:
the first memory device operates in response to a first command latch enable signal, a first address latch enable signal, a first write enable signal, a first read enable signal, and a plurality of first data signals provided through the first memory interface,
the second memory device operates in response to a second command latch enable signal, a second address latch enable signal, a second write enable signal, a second read enable signal, and a plurality of second data signals provided through the second memory interface, and
a number of the plurality of second data signals is more than a number of the plurality of first data signals.

4. The storage device of claim 1 , wherein:
the first memory device includes a plurality of first data signal pins connected with the first memory interface,
the second memory device includes a plurality of second data signal pins connected with the second memory interface, and
a number of the second data signal pins is more than a number of the first data signal pins.

5. The storage device of claim 1 , wherein:
the plurality of first memory cells of the first memory device are divided into a plurality of first planes, and the plurality of second memory cells of the second memory device are divided into a plurality of second planes, and
a number of the second planes is more than a number of the first planes.

6. The storage device of claim 1 , further comprising a third memory device including a plurality of third memory cells having a same type as the plurality of first memory cells and configured to communicate with the second controller through a third memory interface.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yoo Younggeon
• Seol Changkyu
• Kim Hyeonwu
• Song Hyeongseok

Classifications

• G06F3/064 Primary

  Management of blocks · CPC title

• G06F3/061 Primary

  Improving I/O performance · CPC title

• G06F3/0658

  Controller construction arrangements · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title