Continuous-time input-stage successive approximation register analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-11757461-B2
Application number	US-202017638980-A
Country	US
Kind code	B2
Filing date	Feb 12, 2020
Priority date	Aug 28, 2019
Publication date	Sep 12, 2023
Grant date	Sep 12, 2023

Abstract

The exemplified disclosure presents a successive approximation register analog-to-digital converter circuit that comprises a two-step (e.g., two-stage) analog-to-digital converter (ADC) that operates a 1st-stage successive approximation register (SAR) in the continuous time (CT) domain (also referred to as a “1-st stage CTSAR”) that then feeds a sampling operation location in the second stage. Without a front-end sampling circuit in the 1st-stage, the exemplary successive approximation analog-to-digital converter circuit can avoid high sampling noise associated with such sampling operation and thus can be configured with a substantially smaller input capacitor size (e.g., at least 20 times smaller) as compared to conventional Nyquist ADC with a front-end sample-and-hold circuit.

First claim

What is claimed is:

1. An analog-to-digital converter (ADC) comprising:
a first successive approximation register circuit configured to perform a plurality of successive continuous-time approximations of an input waveform to generate, at an output of the first successive approximation register circuit, a continuous-time residue signal and a first set of converted outputs, wherein the first successive approximation register circuit is configured to simultaneously perform input tracking and successive approximation register quantization;
a sampling circuit coupled to the output of the first successive approximation register circuit to sample and hold the continuous-time residue signal after the successive continuous-time approximations; and
a second successive approximation register circuit coupled to an output of the sampling circuit to perform a plurality of successive discrete-time approximations of the sampled residue signal to generate a second set of converted outputs, wherein the first set of converted outputs and the second set of converted outputs are used to generate an output of the analog-to-digital converter.

2. The analog-to-digital converter (ADC) of claim 1 , further comprising:
an inter-stage amplifier serially located between the output of the first successive approximation register and the sampling circuit, the inter-stage amplifier being configured as a low-pass filter.

3. The analog-to-digital converter (ADC) of claim 2 , wherein the inter-stage amplifier is configured as a floating inverter-based (FIB) dynamic amplifier (DA) configured with a linear integration operation and a positive-feedback regeneration operation.

4. The analog-to-digital converter (ADC) of claim 2 , wherein the inter-stage amplifier comprises a filter circuit and a gain amplifier circuit.

5. The analog-to-digital converter (ADC) of claim 1 , wherein the second successive approximation register circuit comprises redundancy of the first successive approximation register circuit, the analog-to-digital converter further comprising:
a summing circuit coupled to the first successive approximation register circuit and the second successive approximation register circuit, wherein the summing circuit is configured to perform a weighted sum operation of at least a portion the first set of converted outputs and at least a portion of the second set of converted outputs.

6. The analog-to-digital converter (ADC) of claim 1 , wherein the first successive approximation register circuit and the second successive approximation register circuit are capacitively-coupled.

7. The analog-to-digital converter (ADC) of claim 1 , wherein the analog-to-digital converter are implemented, in part, using at least one of CMOS, NMOS, PMOS process.

8. The analog-to-digital converter (ADC) of claim 1 , wherein the ADC is configured as at least one of an 8-bit ADC, a 9-bit ADC, a 10-bit ADC, a 11-bit ADC, a 12-bit ADC, a 13-bit ADC, a 14-bit ADC, a 15-bit ADC, a 16-bit ADC, a 17-bit ADC, a 18-bit ADC, a 19-bit ADC, a 20-bit ADC, a 21-bit ADC, a 22-bit ADC, a 23-bit ADC, and a 24-bit ADC.

9. The analog-to-digital converter (ADC) of claim 1 , wherein the first successive approximation register circuit comprises an input capacitor, the input capacitor having a capacitance less than 120 fF for a 13-bit conversion.

10. The analog-to-digital converter (ADC) of claim 1 , wherein the first successive approximation register circuit comprises an input capacitor, the input capacitor being sub-pico-Farad.

11. The analog-to-digital converter (ADC) of claim 1 , wherein the first successive approximation register circuit forms a CT-SAR based 1st-stage that does not include a sample-and-hold circuit.

12. The analog-to-digital converter (ADC) of claim 1 , wherein the first successive approximation register circuit is configured to perform a single-bit comparison, a single-bit DAC, and a subtraction operation for each respective CT-SAR cycle.

13. A method of converting an input analog signal to an output digital signal representing the input analog signal, the method comprising:
successively approximating, via a circuit, over a first set of plurality of approximations, a residue signal of the input analog signal to determine a first set of converted outputs of the digital signal, wherein at each first set of plurality of approximations one or more additional converted outputs of the first set of converted outputs are determined and an aggregated set of the generated first set of converted outputs bits is used to generate a signal that is combined to the input analog signal;
sampling, via the circuit, the residual signal after the plurality of approximations the residue signal;
successively approximating, via the circuit, over a second set of plurality of approximations, the sampled residue signal to determine a second set of converted outputs of the digital signal;
simultaneously performing both input tracking and SAR quantization over the first set of plurality of approximations as a part of the step to successively approximating the residue signal of the input analog signal;
combining, via the circuit, the first set of converted outputs and the second set of converted outputs to generate the output digital signal representing the input analog signal; and
outputting, via the circuit, the output digital signal.

14. The method of claim 13 , wherein the steps are performed within a single ADC conversion cycle.

15. The method of claim 13 , wherein the step of simultaneously performing both input tracking comprises:
adding, via the circuit, at each of the first set of plurality of approximations after a first approximation, the successively approximated residue signal of the input analog signal to the input signal analog signal while allowing the input analog signal to float.

16. The method of claim 13 , further comprising:
performing, via the circuit, a low-pass operation prior to the sampling step and after the successively approximating step to generate the residue signal.

17. The method of claim 13 , further comprising:
performing, via the circuit, a low-pass and gain operation prior to the sampling step and after the successively approximating step to generate the residue signal.

18. The method of claim 13 , wherein the step of successively approximating the sampled residue signal to determine a second set of converted outputs comprises redundancy of the first successive approximation operation, the method further comprising:
performing, via the circuit, a weighted sum operation of at least a portion the first set of converted outputs and at least a portion of the second set of converted outputs.

19. An analog-to-digital converter (ADC) or electric circuit comprising:
a first successive approximation register circuit configured to perform a plurality of successive continuous-time approximations of an input waveform to generate, at an output of the first successive approximation register circuit, a continuous-time residue signal and a first set of converted outputs;
a sampling circuit coupled to the output of the first successive approximation register circuit to sample and hold the continuous-time residue signal after the successive continuous-time approximations;
a second successive approximation register circuit coupled to an output of the sampling circuit to perform a plurality of successive discrete-time approximations of the sampled residue signal to generate a second set of converted outputs, wherein the first set of converted outputs and the second set of converted outputs are

Assignees

• Univ Texas

Inventors

• Shen Linxiao
• Sun Nan

Classifications

• G11C27/024 Primary

  using a capacitive memory element (G11C27/04 takes precedence) · CPC title

• H03M1/0695 Primary

  using less than the maximum number of output states per stage or step, e.g. 1.5 per stage or less than 1.5 bit per stage type · CPC title

• H03M1/164

  the steps being performed sequentially in series-connected stages (H03M1/161 takes precedence) · CPC title

• H03M1/468

  in which the input S/H circuit is merged with the feedback DAC array · CPC title

• H03M1/10

  Calibration or testing · CPC title