High performance fast Mux-D scan flip-flop

Patent metadata

Field	Value
Publication number	US-11757434-B2
Application number	US-202217711638-A
Country	US
Kind code	B2
Filing date	Apr 1, 2022
Priority date	Dec 23, 2019
Publication date	Sep 12, 2023
Grant date	Sep 12, 2023

Abstract

A fast Mux-D scan flip-flop is provided, which bypasses a scan multiplexer to a master keeper side path, removing delay overhead of a traditional Mux-D scan topology. The design is compatible with simple scan methodology of Mux-D scan, while preserving smaller area and small number of inputs/outputs. Since scan Mux is not in the forward critical path, circuit topology has similar high performance as level-sensitive scan flip-flop and can be easily converted into bare pass-gate version. The new fast Mux-D scan flip-flop combines the advantages of the conventional LSSD and Mux-D scan flip-flop, without the disadvantages of each.

First claim

What is claimed is:

1. An apparatus comprising:
a latch that includes a data path and a scan path, wherein the latch includes:
a transmission gate coupled on the data path between a data input and a keeper node; and
a memory circuitry coupled to the keeper node, wherein the scan path is coupled to the memory circuitry, wherein the memory circuitry includes:
a first tri-statable inverter having an input coupled to the keeper node; and
a second tri-statable inverter having an input coupled to an output of the first tri-statable inverter and the scan path, wherein an output of the second tri-statable inverter is coupled to the keeper node; and

scan clock circuitry to generate scan clock signals for a scan mode of the latch, the scan clock circuitry comprising:
an inverter having an input and an output, wherein an input of the inverter is to receive an input clock;
an AND logic coupled to the output of the inverter, wherein the AND logic is to receive a scan select signal; and
an OR logic coupled to the input of the inverter, wherein the OR logic is to receive the scan select signal.

2. The apparatus of claim 1 , wherein the scan path includes a third tri-statable inverter with an input coupled to a scan input and an output coupled to the input of the second tri-statable inverter.

3. The apparatus of claim 2 , wherein the scan clock signals are to control the first, second, and third tri-statable inverters.

4. The apparatus of claim 3 , wherein the scan clock signals are further to control the transmission gate.

5. The apparatus of claim 1 , wherein the latch is a primary latch, and wherein the apparatus further comprises a secondary latch coupled to the primary latch.

6. The apparatus of claim 5 , wherein the inverter is a first inverter, and wherein the apparatus further comprises a second inverter coupled between the keeper node and an input of the secondary latch.

7. The apparatus of claim 1 , wherein the inverter is a first inverter, and wherein the data path includes:
a second inverter to receive an input data; and
a third inverter coupled in series with the second inverter, wherein the third inverter is coupled to the transmission gate.

8. The apparatus of claim 1 , wherein the transmission gate is to directly receive a data input without intervening buffers or inverters.

9. An apparatus comprising:
a primary latch that includes:
a data path and a scan path;
a transmission gate coupled on the data path between a data input and a keeper node;
a memory circuitry coupled to the keeper node, wherein the scan path is coupled to the memory circuitry; and
a tri-statable inverter on the scan path with an input coupled to a scan input and an output coupled to the memory circuitry;

a first inverter with an input coupled to the keeper node;
a secondary latch with an input coupled to an output of the inverter; and
scan clock circuitry to generate scan clock signals to control the transmission gate, the memory circuitry, and the tri-statable inverter for a scan mode of the apparatus, wherein the scan clock circuitry includes:
a second inverter having an input and an output, wherein an input of the second inverter is to receive an input clock;
an AND logic coupled to the output of the second inverter, wherein the AND logic is to receive a scan select signal; and
an OR logic coupled to the input of the second inverter, wherein the OR logic is to receive the scan select signal.

10. The apparatus of claim 9 , wherein the tri-statable inverter is a first tri-statable inverter, and wherein the memory circuitry includes:
a second tri-statable inverter having an input coupled to the keeper node; and
a third tri-statable inverter having an input coupled to an output of the first tri-statable inverter and the scan path, wherein an output of the third tri-statable inverter is coupled to the keeper node, and wherein the scan clock signals are to control the second and third tri-statable inverters.

11. The apparatus of claim 10 , wherein the output of the first tri-statable inverter is coupled to the input of the third tri-statable inverter.

12. The apparatus of claim 9 , wherein the inverter is a first inverter, and wherein the data path includes:
a second inverter to receive an input data; and
a third inverter coupled in series with the second inverter, wherein the third inverter is coupled to the transmission gate.

13. The apparatus of claim 9 , wherein the transmission gate is to directly receive a data input without intervening buffers or inverters.

14. A system comprising:
a wireless communication interface;
a memory; and
a processor coupled to the memory and the wireless communication interface, the processor having a flip-flop that includes:
a primary latch that includes a data path and a scan path, wherein the primary latch includes:
a transmission gate coupled on the data path between a data input and a keeper node; and
a memory circuitry coupled to the keeper node, wherein the scan path is coupled to the memory circuitry, wherein the memory circuitry includes:
a first tri-statable inverter having an input coupled to the keeper node; and
a second tri-statable inverter having an input coupled to an output of the first tri-statable inverter and the scan path, wherein an output of the second tri-statable inverter is coupled to the keeper node;

a secondary latch coupled to an output of the primary latch; and
scan clock circuitry to generate scan clock signals to control the primary latch, wherein the scan clock circuitry includes:
an inverter having an input and an output, wherein an input of the inverter is to receive an input clock;
an AND logic coupled to the output of the inverter, wherein the AND logic is to receive a scan select signal; and
an OR logic coupled to the input of the inverter, wherein the OR logic is to receive the scan select signal.

15. The system of claim 14 , wherein the scan path includes a third tri-statable inverter with an input coupled to a scan input and an output coupled to the input of the second tri-statable inverter.

16. The system of claim 15 , wherein the scan clock signals are to control the first, second, and third tri-statable inverters.

17. The system of claim 16 , wherein the scan clock signals are further to control the transmission gate.

Assignees

• Intel Corp

Inventors

• Agarwal Amit
• Hsu Steven
• REALOV Simeon
• Kumashikar Mahesh
• Krishnamurthy Ram

Classifications

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• H03K3/0372 Primary

  of the primary-secondary type · CPC title

• G11C29/12015

  comprising clock generation or timing circuitry · CPC title

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G06F11/0757

  by exceeding a time limit, i.e. time-out, e.g. watchdogs · CPC title