Integrated circuit and design method for same

Patent metadata

Field	Value
Publication number	US-9928337-B2
Application number	US-201615376261-A
Country	US
Kind code	B2
Filing date	Dec 12, 2016
Priority date	Apr 26, 2016
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

A computer-implemented method for designing an integrated circuit includes: performing a simulation on input data or an initial layout to determine whether or not a design constraint has been violated. Upon determining that the design constraint has been violated, a redesign layout is created by adding a cutting area without changing a size of the integrated circuit. The adding a cutting area separates at least one of an active region and a gate line. At least one of the initial layout and the redesign layout is stored in a non-transitory computer readable storage medium.

First claim

What is claimed is:

1. A computer-implemented method for designing an integrated circuit, the method comprising:
receiving input data defining the integrated circuit characterized by at least one design constraint;
performing a simulation using the input data to determine whether or not the at least one design constraint has been violated;
upon determining that the at least one design constraint has not been violated, creating an initial layout based on the input data, wherein the initial layout includes at least one active area and at least one gate line and defines a size of the integrated circuit;
upon determining that the at least one design constraint has been violated, creating a redesign layout by adding at least one cutting area to the initial layout without changing the size of the integrated circuit, wherein the adding at least one cutting area separates at least one of the at least one active area, and the at least one gate line; and
storing at least one of the initial layout and the redesign layout in a non-transitory computer readable storage medium.

2. The method of claim 1 , wherein the simulation is a timing analysis, the at least one design constraint is a plurality of timing constraints including a hold time and a setup time for a data input signal in relation to a clock signal.

3. The method of claim 2 , wherein the integrated circuit is a scan flip-flop,
the at least one active area comprises a first active region and a second active region extending in a first direction, the first active region having a first conductivity type and the second active region having a second conductivity type different from the first conductivity type, and
the at least one gate line comprises a first gate line, a second gate line, and a third gate line extending in a second direction substantially perpendicular to the first direction, the first gate line corresponding to a data input pin receiving the data input signal and being disposed across the first active region and the second active region, the second gate line corresponding to a scan input pin and being disposed across the first active region and the second active region, and the third gate line being disposed across the second active region.

4. The method of claim 3 , wherein the creating a redesign layout comprises:
adding a dummy gate load on at least one of the data input pin and the scan input pin.

5. The method of claim 4 , wherein the adding at least one cutting area to the initial layout comprises:
adding a first cutting area to separate a partial region adjacent to the first gate line in the first active region;
adding a first new gate line corresponding to the dummy gate load on the first cutting area; and
connecting the first gate line to the first new gate line.

6. The method of claim 5 , wherein the at least one gate line further comprises a fourth gate line adjacent to the second gate line,
the adding at least one cutting area to the initial layout comprises:
adding a second cutting area to separate a lower portion of the fourth gate line in the second active region, and
adding a third cutting area to separate the fourth gate line into a first partial gate line and a second partial gate line; and

the creating a redesign layout further comprises:
connecting the second gate line to the second partial gate line disposed on the second cutting area and corresponding to the dummy gate load.

7. The method of claim 3 , wherein the creating a redesign layout comprises at least one of:
adding a first series stacked transistor to the initial layout proximate to the data input pin; and
adding a second series stacked transistor to the initial layout proximate to the scan input pin.

8. The method of claim 7 , wherein the creating a redesign layout further comprises:
adding a first new gate line adjacent to the first gate line and constituting the first series stacked transistor on the first active region; and
connecting the first gate line to the first new gate line.

9. The method of claim 8 , wherein the at least one gate line comprises a fourth gate line adjacent to the second gate line, and a second cutting area separates a lower portion of the fourth gate line in the second active region, and
the creating a redesign layout comprises:
adding a third cutting area to separate the fourth gate line into a first partial gate line and a second partial gate line;
adding a first new active region under the second partial gate line on the second cutting area; and
connecting the second gate line to the second partial gate line,
wherein the second partial gate line and the first new active region constitute the second series stacked transistor.

10. The method of claim 3 , wherein the creating a redesign layout comprises at least one of:
adding a first parallel stacked transistor to the initial layout proximate to the data input pin; and
adding a second parallel stacked transistor to the initial layout proximate to the scan input pin.

11. The method of claim 1 , wherein the at least one design constraint comprises a power noise constraint, and the performing a simulation comprises:
performing a power analysis using the input data; and
determining whether the power noise constraint has been violated.

12. The method of claim 1 , wherein the initial layout comprises a dummy gate line, and the creating a redesign layout comprises adding a decoupling capacitor using the dummy gate line.

13. The method of claim 12 , wherein the creating a redesign layout further comprises:
adding a first cutting area to separate the dummy gate line into a first partial dummy gate line and a second partial dummy gate line;
adding a first new active region extending in a first direction under the first partial dummy gate line;
adding a second new active region extending in the first direction under the second partial dummy gate line;
forming contacts connected to a power supply voltage terminal at both sides of the first partial dummy gate line in the first new active region;
forming contacts connected to a ground voltage terminal at both sides of the second partial dummy gate line in the second new active region;
forming a contact pattern connected to the ground voltage terminal on the first partial dummy gate line; and
forming a contact pattern connected to the power supply voltage terminal on the second partial dummy gate line.

14. A computer-implemented method for designing an integrated circuit, the method comprising:
designing an initial layout for the integrated circuit to incorporate a standard cell by referencing the standard cell in a standard cell library stored in a non-transitory computer readable storage medium,
wherein the standard cell comprises:
a first active region, a second active region and a third active region extending in a first direction;
gate lines extending in a second direction substantially perpendicular to the first direction;
a dummy gate line extending in parallel with the gate lines; and
source/drain contacts disposed on opposing sides of the dummy gate line,
wherein the source/drain contacts are disposed on the third active region and having a same voltage applied thereto, and
the third active region is disposed under the dummy gate line, such that a combination of the dummy gate line and the third active region constitutes a decoupling capacitor within the integrated circuit.

15. The method of claim 14 , further comprising:
redesigning the initial layout to create a redesign layout upon determining that the initial layout violates a design constraint established for the integrated cir

Assignees

• Samsung Electronics Co Ltd

Inventors

• Gothi Abhishek
• Srinivasa Kodanda Rama Reddy

Classifications

• G06F2111/20

  Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• H03K3/35625

  using complementary field-effect transistors · CPC title

• G06F17/5031

  Physics · mapped topic