High bandwidth module

Patent metadata

Field	Value
Publication number	US-11756930-B2
Application number	US-202117520718-A
Country	US
Kind code	B2
Filing date	Nov 8, 2021
Priority date	Mar 10, 2020
Publication date	Sep 12, 2023
Grant date	Sep 12, 2023

Abstract

A module includes a substrate having a plurality of contact regions, and a spacer-chip assembly. The spacer-chip assembly in turn includes at least first and second semiconductor dies, each having a plurality of electrical interconnect pillars and a plurality of contact pads, and a spacer wafer. The at least first and second semiconductor dies are secured to the spacer wafer, and the spacer wafer includes at least first and second semiconductor circuit features coupled to a first portion of the contact pads of the at least first and second semiconductor dies. The spacer wafer includes wiring electrically coupling the at least first and second semiconductor dies via a second portion of the contact pads. The spacer wafer has a plurality of holes formed therethrough. The plurality of electrical interconnect pillars extend through the holes and are secured to the contact regions on the substrate.

First claim

What is claimed is:

1. A method comprising:
providing a spacer wafer, said spacer wafer having inner and outer surfaces, said spacer wafer including at least first and second semiconductor circuit features and wiring, adjacent said outer surface;
forming a plurality of trenches partially through said spacer wafer, spaced from said at least first and second semiconductor circuit features and said wiring;
providing first and second semiconductor dies, each having a plurality of electrical interconnect pillars and a plurality of contact pads, said electrical interconnect pillars having distal ends;
securing said first and second semiconductor dies to said spacer wafer via said plurality of contact pads with said interconnect pillars extending into said trenches, and with said contact pads coupled to said wiring and said semiconductor circuit features, to form a spacer-chip assembly;
processing said inner surface of said of said spacer wafer to open said trenches and expose said distal ends of said pillars;
applying electrically conductive connective material to said distal ends of said pillars; and
securing said spacer-chip assembly to a substrate via said electrically conductive connective material on said distal ends of said pillars.

2. The method of claim 1 , wherein applying said electrically conductive connective material comprises applying dippable paste.

3. The method of claim 2 , wherein said semiconductor circuit features comprise decoupling capacitors.

4. The method of claim 3 , further comprising applying underfill material into said trenches subsequent to said securing.

5. The method of claim 4 , further comprising applying over-molding over and between said first and second semiconductor dies after applying said underfill.

6. The method of claim 5 , further comprising processing said over-molding to render it flush with outer surfaces of said semiconductor dies.

7. The method of claim 6 , wherein:
said providing further comprises providing third and fourth semiconductor dies, each having a plurality of electrical interconnect pillars and a plurality of contact pads;
said securing further comprises securing said third and fourth semiconductor dies to said spacer wafer via said plurality of contact pads with said interconnect pillars extending into said trenches, and with said contact pads coupled to said wiring, to form said spacer-chip assembly;
further comprising singulating said spacer wafer to form a first module including said first and second semiconductor dies and a second module including said third and fourth semiconductor dies.

8. The method of claim 7 , further comprising partially dicing said spacer-chip assembly by forming cuts from outside into said spacer wafer, prior to processing said inner surface, wherein said processing of said inner surface of said spacer wafer effectuates said singulating via contacting said cuts.

9. The method of claim 8 , wherein said partial dicing comprises plasma dicing.

10. The method of claim 5 , further comprising:
forming a pocket in said spacer wafer; and
adhering glass into said pocket;
wherein:
said forming of said plurality of trenches includes forming at least a portion of said trenches in said glass;
said first semiconductor die comprises a silicon chip;
said second semiconductor die comprises a silicon carbide chip; and
in said step of securing said first and second semiconductor dies to said spacer wafer via said plurality of contact pads with said interconnect pillars extending into said trenches, at least a portion of those of said interconnect pillars associated with said silicon carbide chip extend into those of said trenches in said glass.

11. The method of claim 1 , wherein applying said electrically conductive connective material comprises applying controlled collapse chip connection (C4) solder blobs.

Assignees

• IBM

Inventors

• Arvin Charles Leon
• Singh Bhupender
• Li Shidong
• Muzzy Chris
• Wassick Thomas Anthony

Classifications

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W74/114

  by a substrate and the encapsulations · CPC title

• H10W74/01

  Manufacture or treatment · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title