Storage system and method for operating storage system based on buffer utilization

US11755241B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11755241-B2
Application numberUS-202117548889-A
CountryUS
Kind codeB2
Filing dateDec 13, 2021
Priority dateDec 14, 2020
Publication dateSep 12, 2023
Grant dateSep 12, 2023

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A storage device includes a buffer memory configured to temporarily store data; a plurality of nonvolatile memory devices; a storage controller circuit configured to generate buffer memory status information by monitoring a status of the buffer memory and operating in a congestion control mode of setting a buffer memory data transmission authority of a nonvolatile memory based on the generated buffer memory status information; and a first interface circuit configured to communicate with the storage controller circuit and the plurality of nonvolatile memory devices, wherein the first interface circuit is connected to a network based on an Ethernet interface.

First claim

Opening claim text (preview).

What is claimed is: 1. A storage device comprising: a buffer memory configured to temporarily store data; a plurality of nonvolatile memory devices; a storage controller circuit configured to generate buffer memory status information by monitoring a status of the buffer memory, operate in a congestion control mode by setting a buffer memory data transmission authority of a nonvolatile memory device based on the generated buffer memory status information, generate data tokens based on a utilization rate of the buffer memory, allocate the data tokens to the plurality of nonvolatile memory devices based on a priority table, the priority table indicating data transmission priorities of the plurality of nonvolatile memory devices, and control data transmission of the plurality of nonvolatile memory devices according to the allocated data tokens; and a first interface circuit configured to communicate with the storage controller circuit and the plurality of nonvolatile memory devices, wherein the first interface circuit is connected to a network based on an Ethernet interface. 2. The storage device of claim 1 , wherein the plurality of nonvolatile memory devices are configured to perform data transmission rate control based on information including the buffer memory data transmission authority, which is received from the storage controller circuit. 3. The storage device of claim 1 , wherein the storage controller circuit is configured to control data transmission of the plurality of nonvolatile memory devices based on the priority table. 4. The storage device of claim 3 , wherein the priority table further includes a weight for each nonvolatile memory device, which is set based on a data request order and a requested data amount. 5. The storage device of claim 1 , wherein the storage controller circuit is configured to control the data transmission of the plurality of nonvolatile memory devices according to a preset scheduling scheme based on the priority table and the data tokens. 6. The storage device of claim 1 , wherein the storage controller circuit is configured such that the storage controller circuit has a first stage of operating in a congestion control mode when a utilization rate of the buffer memory is greater than a first limit value, and a second stage of temporarily suspending data transmission when the utilization rate of the buffer memory is greater than a second limit value. 7. The storage device of claim 1 , wherein the storage controller circuit is configured to control at least one a bandwidth, a data transmission rate, or a power consumption amount of the first interface circuit based on the utilization rate of the buffer memory. 8. The storage device of claim 1 , further comprising: a second interface circuit configured to control a data transmission amount of the plurality of nonvolatile memory devices through the storage controller circuit. 9. The storage device of claim 1 , wherein the storage controller circuit is configured to, estimate utilization rate of the buffer memory by monitoring input and output data and a data transmission rate of the buffer memory, and operate in congestion control mode based on the estimated utilization rate of the buffer memory. 10. A method of operating a storage device, the method comprising: generating buffer memory status information by monitoring a status of a buffer memory; setting a data transmission mode of a plurality of nonvolatile memory devices based on the generated buffer memory status information; controlling the plurality of nonvolatile memory devices based on the set data transmission mode; generating data tokens based on a utilization rate of the buffer memory; allocating the data tokens to the plurality of nonvolatile memory devices based on a priority table, the priority table indicating data transmission priorities of the plurality of nonvolatile memory devices; and controlling data transmission of the plurality of nonvolatile memory devices according to the allocated data tokens, wherein the data transmission mode includes a congestion control mode including setting a data transmission authority of a nonvolatile memory device in response to the utilization rate of the buffer memory being greater than a preset reference value. 11. The method of claim 10 , wherein the controlling includes controlling data transmission of the plurality of nonvolatile memory devices based on the priority table. 12. The method of claim 11 , wherein the priority table includes a weight for each nonvolatile memory device, which is set based on a data request order and a requested data amount. 13. The method of claim 12 , wherein the controlling further comprises: controlling the data transmission of the plurality of nonvolatile memory devices according to a preset scheduling scheme based on the priority table and the data tokens. 14. The method of claim 10 , further comprising: communicating with a storage controller circuit and the plurality of nonvolatile memory devices by using a first interface circuit, wherein the first interface circuit is connected to a network based on an Ethernet interface. 15. The method of claim 10 , wherein the controlling comprises: controlling a bandwidth, a data transmission rate, or a power consumption amount of a first interface circuit based on the utilization rate of the buffer memory. 16. The method of claim 10 , further comprising: controlling a data transmission amount of the plurality of nonvolatile memory devices through a second interface circuit. 17. The method of claim 10 , wherein the controlling comprises: estimating the utilization rate of the buffer memory by monitoring input and output data and a data transmission rate of the buffer memory; and operating in the congestion control mode based on the estimated utilization rate of the buffer memory. 18. A non-transitory computer-readable recording medium having recorded thereon computer-readable instructions that, when executed by one or more processors, cause the one or more processors to perform operations including: generating buffer memory status information by monitoring a status of a buffer memory; setting a data transmission mode of a plurality of nonvolatile memory devices based on the generated buffer memory status information; controlling the plurality of nonvolatile memory devices based on the set data transmission mode; generating data tokens based on a utilization rate of the buffer memory; allocating the data tokens to the plurality of nonvolatile memory devices based on a priority table, the priority table indicating data transmission priorities of the plurality of nonvolatile memory devices; and controlling data transmission of the plurality of nonvolatile memory devices according to the allocated data tokens, wherein the data transmission mode includes a congestion control mode including setting a data transmission authority of a nonvolatile memory device in response to the utilization rate of the buffer memory being greater than a preset reference value.

Assignees

Inventors

Classifications

  • for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS] · CPC title

  • G06F3/061Primary

    Improving I/O performance · CPC title

  • G06F3/067Primary

    Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS] · CPC title

  • G06F3/0656Primary

    Data buffering arrangements · CPC title

  • using leaky-bucket · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US11755241B2 cover?
A storage device includes a buffer memory configured to temporarily store data; a plurality of nonvolatile memory devices; a storage controller circuit configured to generate buffer memory status information by monitoring a status of the buffer memory and operating in a congestion control mode of setting a buffer memory data transmission authority of a nonvolatile memory based on the generated …
Who is the assignee on this patent?
Samsung Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification H04L67/1097. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 12 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 9 related publications on this page (citations in our corpus or others sharing the same primary CPC).