Hetergenous integration and electro-optic modulation of III-nitride photonics on a silicon photonic platform

US11754865B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11754865-B2
Application numberUS-202016953574-A
CountryUS
Kind codeB2
Filing dateNov 20, 2020
Priority dateNov 22, 2019
Publication dateSep 12, 2023
Grant dateSep 12, 2023

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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Abstract

Official abstract text for this publication.

A photonic integrated circuit comprises a silicon nitride waveguide, an electro-optic modulator formed of a III-nitride waveguide structure disposed on the silicon nitride waveguide, a dielectric cladding covering the silicon nitride waveguide and electro-optic modulator, and electrical contacts disposed on the dielectric cladding and arranged to apply an electric field to the electro-optic modulator.

First claim

Opening claim text (preview).

What is claimed is: 1. A photonic integrated circuit comprising: a silicon nitride waveguide; an electro-optic modulator formed of a III-nitride waveguide structure disposed on the silicon nitride waveguide, the III-nitride waveguide structure bonded to the silicon nitride waveguide with a III-nitride slab; a silicon dioxide layer disposed on a substrate, the silicon nitride waveguide disposed on the silicon dioxide layer beneath the III-nitride waveguide, the III-nitride slab supported above the silicon dioxide layer by the silicon nitride waveguide and by silicon nitride support layers disposed on the silicon dioxide layer and separated laterally from the silicon nitride waveguide in a direction perpendicular to a direction of light passage through the silicon nitride waveguide and III-nitride waveguide; a dielectric cladding covering the silicon nitride waveguide and electro-optic modulator; and electrical contacts disposed on the dielectric cladding and arranged to apply an electric field to the electro-optic modulator. 2. The photonic integrated circuit of claim 1 , wherein the III-nitride waveguide structure is formed of one of Al x Ga 1-x N (0≤x≤1), In x Ga 1-x N (0≤x≤1), or Al x In 1-x N (0≤x≤1). 3. The photonic integrated circuit of claim 1 , wherein the III-nitride waveguide structure includes a stacked layer of quantum wells formed of one of Al x Ga 1-z N (0≤x≤1), In x Ga 1-z N (0≤x≤1), or Al x In 1-z N (0≤x≤1). 4. The photonic integrated circuit of claim 1 , wherein the III-nitride waveguide structure is bonded to the silicon nitride waveguide and the silicon nitride support layers with the III-nitride slab. 5. The photonic integrated circuit of claim 1 , wherein the dielectric cladding is formed of silicon dioxide. 6. The photonic integrated circuit of claim 1 , further comprising one or more heterogeneously integrated III-nitride quantum well modulators. 7. The photonic integrated circuit of claim 1 , further comprising a photodetector. 8. The photonic integrated circuit of claim 7 , wherein the photodetector is optically coupled to the silicon nitride waveguide. 9. The photonic integrated circuit of claim 7 , wherein the photodetector is disposed on a same side of the silicon nitride waveguide as the dielectric cladding. 10. The photonic integrated circuit of claim 7 , wherein the photodetector is disposed on a opposite side of the silicon nitride waveguide as the dielectric cladding. 11. The photonic integrated circuit of claim 7 , further comprising a conductive via passing through the dielectric cladding and forming an electrical path between a contact pad of the photodetector and an external contact pad disposed on a surface of the dielectric cladding. 12. The photonic integrated circuit of claim 1 , further comprising a conductive via passing through the dielectric cladding and forming an electrical path between the III-nitride waveguide structure and an external contact pad disposed on a surface of the dielectric cladding. 13. The photonic integrated circuit of claim 1 , wherein the III-nitride waveguide structure has a tapered end portion. 14. The photonic integrated circuit of claim 1 , wherein the III-nitride waveguide is wider than the silicon nitride waveguide. 15. The photonic integrated circuit of claim 1 , wherein the III-nitride waveguide has greater height than the III-nitride slab. 16. The photonic integrated circuit of claim 1 , further comprising a layer of silicon dioxide disposed between the III-nitride slab and the silicon nitride waveguide.

Assignees

Inventors

Classifications

  • Three-dimensional structures · CPC title

  • G02F1/0553Primary

    specially adapted for gating or modulating in optical waveguides · CPC title

  • Modulator · CPC title

  • using electro-optic effects, e.g. linear electro optic [LEO], Pockels, quadratic electro optical [QEO] or Kerr effect · CPC title

  • Constructional details · CPC title

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What does patent US11754865B2 cover?
A photonic integrated circuit comprises a silicon nitride waveguide, an electro-optic modulator formed of a III-nitride waveguide structure disposed on the silicon nitride waveguide, a dielectric cladding covering the silicon nitride waveguide and electro-optic modulator, and electrical contacts disposed on the dielectric cladding and arranged to apply an electric field to the electro-optic mod…
Who is the assignee on this patent?
Raytheon Bbn Technologies Corp
What technology area does this patent fall under?
Primary CPC classification G02B6/12002. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Sep 12 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 11 related publications on this page (citations in our corpus or others sharing the same primary CPC).