Stability of bit generating cells through aging

Patent metadata

Field	Value
Publication number	US-11750192-B2
Application number	US-202117546438-A
Country	US
Kind code	B2
Filing date	Dec 9, 2021
Priority date	Feb 24, 2021
Publication date	Sep 5, 2023
Grant date	Sep 5, 2023

Abstract

Bit generating cells are subjected to processes that accelerate aging-related characteristics before they are configured for use in the field (enrolled). Aging improves the reliability of the cells by shifting device characteristic in a direction that improves the cell behavior with respect not only to aging but also environment variations. Outputs of the cells are read, and the cells are reconfigured with a bias to output an opposite value, and then aged for enrollment.

First claim

What is claimed is:

1. A method of operating a circuit, the method comprising:
reading output values of a bit pattern generating circuit comprising physically unclonable function (PUF) cells under an a first condition and under a second condition;
wherein the first condition is one of a biased condition and an unbiased condition, and the second condition is the other;
identifying particular PUF cells of the bit pattern generating circuit that flipped the output values between the first condition and the second condition; and
subjecting at least some of the particular PUF cells to accelerated aging to generate aged cells.

2. The method of claim 1 , wherein subjecting at least some of the particular PUF cells to accelerated aging to generate aged cells comprises:
subjecting only the particular PUF cells to accelerated aging to generate aged cells.

3. The method of claim 1 , wherein the bias condition is a setting for a current ratio.

4. The method of claim 1 , wherein the bias condition is a setting to alter timing of an edge propagation through an edge chasing oscillator.

5. The method of claim 1 , further comprising:
setting the bias condition on the particular PUF cells during the accelerated aging.

6. The method of claim 1 , the accelerated aging comprising subjecting the particular PUF cells to a higher than nominal operating voltage, temperature, or both.

7. The method of claim 1 , further comprising:
enabling outputs of PUF cells of the bit pattern generating circuit in the bit pattern, excepting outputs of the particular PUF cells from the bit pattern.

8. The method of claim 7 , further comprising:
reading output values of the aged cells under the unbiased condition;
reading output values of the aged cells under the biased condition; and
identifying particular aged cells that did not flip output values between the biased condition and the unbiased condition; and
enabling outputs of the particular aged cells in the bit pattern, excepting outputs of the aged cells that flipped output values.

9. The method of claim 1 , wherein the PUF cells of the bit pattern generating circuit comprise a plurality of current mirroring cells each generating one bit of the bit pattern.

10. The method of claim 9 , wherein at least one of the current mirroring cells comprises a PMOS stage and an NMOS stage, and wherein the biased condition comprises setting a maximum current ratio on the PMOS stage.

11. The method of claim 9 , wherein at least one of the current mirroring cells comprises a PMOS stage and an NMOS stage, and wherein the biased condition comprises setting a maximum current ratio on the NMOS stage.

12. The method of claim 9 , wherein at least one of the current mirroring cells comprises a PMOS stage and an NMOS stage, and wherein the biased condition comprises setting a maximum current ratio on both of the PMOS stage and the NMOS stage.

13. A circuit comprising:
a physically unclonable function (PUF) cell;
logic configured to:
read an output value of the PUF cell during an unbiased condition;
read the output value under a biased condition; and
subject the PUF cell to accelerated aging on condition that the output value flipped between the unbiased condition and the biased condition.

14. The circuit of claim 13 , wherein the PUF cell is a current mirroring cell and the bias condition is a setting for a current ratio.

15. The circuit of claim 14 , wherein the PUF cell comprises a PMOS stage and an NMOS stage, and wherein the biased condition comprises setting a maximum current ratio on the PMOS stage.

16. The circuit of claim 14 , wherein the PUF cell comprises a PMOS stage and an NMOS stage, and wherein the biased condition comprises setting a maximum current ratio on the NMOS stage.

17. The circuit of claim 13 , wherein the PUF cell is an edge chasing oscillator and the bias condition is a setting to alter timing of an edge propagation through the edge chasing oscillator.

18. The circuit of claim 13 , the logic further configured to set the bias condition on the PUF cell during the accelerated aging.

19. The circuit of claim 13 , the accelerated aging comprising subjecting the particular cells to a higher than nominal operating voltage, temperature, or both.

20. The circuit of claim 13 , the logic further configured to:
enroll the PUF cell to contribute to a generated bit pattern subsequent to the accelerated aging.

21. The circuit of claim 20 , the logic further configured to:
read the output value of the PUF cell subsequent to the accelerated aging under the unbiased condition;
read the output value subsequent to the accelerated aging under the biased condition; and
enroll the PUF cell to contribute to the generated bit pattern on condition that the output value did not flip between the unbiased condition and the biased condition subsequent to the accelerated aging.

Assignees

• Nvidia Corp

Inventors

• Kudva Sudhir Shrikantha
• Nedovic Nikola
• He Yan

Classifications

• H03K19/00315 Primary

  in field-effect transistor circuits · CPC title

• H03K19/018521

  of complementary type, e.g. CMOS · CPC title

• G05F3/26 Primary

  Current mirrors · CPC title

• H03K19/173 Primary

  using elementary logic circuits as components · CPC title

• H03K19/177

  arranged in matrix form · CPC title