Encryption code generation using spin-torque NANO-oscillators

Patent metadata

Field	Value
Publication number	US-9369277-B2
Application number	US-201414325844-A
Country	US
Kind code	B2
Filing date	Jul 8, 2014
Priority date	Jul 8, 2014
Publication date	Jun 14, 2016
Grant date	Jun 14, 2016

Abstract

Embodiments include apparatuses, methods, and systems for generation of an encryption key. In various embodiments, an authentication circuit may include a first bank of spin-torque nano-oscillators (STNOs) including a plurality of STNOs to generate respective oscillation signals and a second bank of STNOs including a plurality of STNOs to generate respective oscillation signals. The authentication circuit may further include a key generation circuit to select a first oscillation signal from the plurality of oscillation signals associated with the first bank of STNOs and a second oscillation signal from the plurality of oscillation signals associated with the second bank of STNOs. The key generation circuit may generate an encryption key based on a frequency of the first oscillation signal and a frequency of the second oscillation signal.

First claim

What is claimed is:

1. An apparatus, comprising:
a first bank of spin-torque nano-oscillators (STNOs) including a plurality of STNOs to generate respective oscillation signals;
a second bank of STNOs including a plurality of STNOs to generate respective oscillation signals; and
a key generation circuit coupled to the first and second banks of STNOs, the key generation circuit to:
select a first oscillation signal from the plurality of oscillation signals associated with the first bank of STNOs;
select a second oscillation signal from the plurality of oscillation signals associated with the second bank of STNOs; and
generate an encryption key based on a first frequency of the first oscillation signal and a second frequency of the second oscillation signal.

2. The apparatus of claim 1 , wherein the key generation circuit includes:
a first multiplexer coupled to the first bank of STNOs to select the first oscillation signal based on a first select signal; and
a second multiplexer coupled to the second bank of STNOs to select the second oscillation signal based on a second select signal.

3. The apparatus of claim 2 , wherein the key generation circuit further includes:
a first counter coupled to the first multiplexer to count transitions in the first oscillation signal for a time period to obtain a first count value;
a second counter coupled to the second multiplexer to count transitions in the second oscillation signal for the time period to obtain a second count value; and
a comparator to compare the first and second count values, wherein the key generation circuit is to generate the encryption key based on the comparison.

4. The apparatus of claim 3 , wherein the comparator is to compare the first and second values by being configured to determine a magnitude of a difference between the first and second count values, and wherein the encryption key includes a plurality of bits having values based on the magnitude of the difference between the first count value and the second count value.

5. The apparatus of claim 4 , wherein the key generation circuit is to overwrite or discard one or more least significant bits of the determined magnitude for generation of the plurality of bits of the encryption key.

6. The apparatus of claim 1 , wherein the key generation circuit is to generate a first portion of the encryption key based on the first frequency and the second frequency, and wherein the key generation circuit is further to:
select a third oscillation signal from the plurality of oscillation signals associated with the first bank of STNOs;
select a fourth oscillation signal from the plurality of oscillation signals associated with the second bank of STNOs; and
generate a second portion of the encryption key based on a third frequency of the third oscillation signal and a fourth frequency of the fourth oscillation signal.

7. The apparatus of claim 6 , wherein the first portion is a single bit having a first value if the first frequency is higher than the second frequency or a second value if the first frequency is lower than the second frequency.

8. The apparatus of claim 1 , wherein the key generation circuit is to generate a first portion of the encryption key based on the first frequency and the second frequency, and wherein the key generation circuit is further to:
generate a plurality of portions of the encryption key, including the first portion, based on a first pre-defined sequence of STNO indices corresponding to respective STNOs of the first bank of STNOs and a second pre-defined sequence of STNO indices corresponding to respective STNOs of the second bank of STNOs.

9. The apparatus of claim 1 , wherein the key generation circuit is further to transmit the encryption key to an authentication server for authentication of the apparatus.

10. The apparatus of claim 1 , wherein the plurality of STNOs of the first bank of STNOs and the plurality of STNOs of the second bank of STNOs are memory cells including respective magnetic tunnel junctions (MTJs) to store data.

11. A method, comprising:
selecting, based on a first select signal, a first oscillation signal from a plurality of oscillation signals associated with respective spin-torque nano-oscillators (STNOs) of a first bank of STNOs;
selecting, based on a second select signal, a second oscillation signal from a plurality of oscillation signals associated with respective STNOs of a second bank of STNOs;
counting, for a time period, a number of transitions in the first oscillation signal to obtain a first count value;
counting, for the time period, a number of transitions in the second oscillation signal to obtain a second count value; and
generating an encryption key based on the first and second count values.

12. The method of claim 11 , wherein the generating the encryption key based on the first and second count values includes generating a first portion of the encryption key based on the first and second count values, and wherein the method further comprises:
generating a plurality of portions of the encryption key, including the first portion, using a pre-defined sequence of the first select signal and the second select signal.

13. The method of claim 12 , wherein the first portion is a single bit having a first value if the first count value is higher than the second count value or a second value if the first count value is lower than the second count value.

14. The method of claim 12 , wherein the first portion is a plurality of bits having values based on a magnitude of a difference between the first and second count values.

15. The method of claim 11 , wherein generating the encryption key includes:
determining a magnitude of a difference between the first count value and the second count value; and
determining a plurality of bits of the encryption key based on the determined magnitude.

16. The method of claim 15 , wherein the determining the plurality of bits of the encryption key includes overwriting or discarding one or more least significant bits of the determined magnitude.

17. A system, comprising:
a display;
a processor coupled to the display;
a memory coupled to the processor, the memory including:
a first bank of STNOs having a plurality of STNOs to generate respective oscillation signals; and
a second bank of STNOs having a plurality of STNOs to generate respective oscillation signals;

a key generation circuit coupled to the memory to generate an encryption key based on the oscillation signals generated by the STNOs of the first and second banks of STNOs.

18. The system of claim 17 , wherein the key generation circuit includes:
a first multiplexer to select a first oscillation signal, based on a value of a first select signal, from the plurality of oscillation signals associated with the first bank of STNOs;
a second multiplexer to select a second oscillation signal, based on a value of a second select signal, from the plurality of oscillation signals associated with the second bank of STNOs;
a first counter to count transitions in the first oscillation signal for a pre-defined time period to obtain a first count value;
a second counter to count transitions in the second oscillation signal for the pre-defined time period to obtain a second count value; and
a processing circuit to generate at least a portion of an encryption key based on the first count value and the second count value.

19. The system of claim 18 , wherein the processing circuit is to generate a single bit of the encryption key using the first and se

Assignees

• Intel Corp

Inventors

• Augustine Charles
• Tokunaga Carlos
• Tschanz James W

Classifications

• G09C1/00 Primary

  Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00) · CPC title

• H04L2209/12

  Details relating to cryptographic hardware or logic circuitry · CPC title

• H04L9/0816

  Key establishment, i.e. cryptographic processes or cryptographic protocols whereby a shared secret becomes available to two or more parties, for subsequent use · CPC title

• H04L2209/24

  Key scheduling, i.e. generating round keys or sub-keys for block encryption · CPC title

• H04L9/0877 Primary

  using additional device, e.g. trusted platform module [TPM], smartcard, USB or hardware security module [HSM] · CPC title