High electron mobility transistor and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-11749740-B2
Application number	US-201916731058-A
Country	US
Kind code	B2
Filing date	Dec 31, 2019
Priority date	Dec 6, 2019
Publication date	Sep 5, 2023
Grant date	Sep 5, 2023

Abstract

A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a first barrier layer on a substrate; forming a p-type semiconductor layer on the first barrier layer; forming a hard mask on the p-type semiconductor layer; patterning the hard mask and the p-type semiconductor layer; and forming a spacer adjacent to the hard mask and the p-type semiconductor layer.

First claim

What is claimed is:

1. A high electron mobility transistor (HEMT), comprising:
a buffer layer on a substrate;
a first barrier layer on the buffer layer;
a p-type semiconductor layer on the first barrier layer;
a spacer adjacent to the p-type semiconductor layer, wherein the spacer is made of a dielectric material, a bottom surface of the spacer is even with a bottom surface of the p-type semiconductor layer, the spacer comprises an inner sidewall and an outer sidewall, and the outer sidewall of the spacer comprises a curve;
a second barrier layer adjacent to the spacer on the first barrier layer, wherein a topmost surface of the second barrier layer is lower than a top surface of the p-type semiconductor layer;
a gate electrode on and directly contacting the p-type semiconductor layer, wherein a width of the gate electrode is less than a width of the p-type semiconductor layer;
a hard mask on the p-type semiconductor layer and laterally around the gate electrode, wherein a bottom surface of the hard mask is even with a bottom surface of the gate electrode, a top surface of the hard mask is lower than a top surface of the gate electrode, and a topmost point of the spacer is at the same level with the top surface of the hard mask and lower than the top surface of the gate electrode; and
a source electrode and a drain electrode adjacent to two sides of the spacer.

2. The HEMT of claim 1 , wherein the hard mask comprises a dielectric material.

Assignees

• United Microelectronics Corp

Inventors

• Chen bo-rong
• Huang Che-Hung
• Chang Chun-Ming
• Hsu Yi-Shan
• Yeh Chih-Tung
• Huang Shin-Chuan
• Liao Wen-Jung
• Hou Chun-Liang

Classifications

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D30/4732

  using Group III-V semiconductor material · CPC title

• H10D30/015 Primary

  of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT · CPC title

• H10D62/824

  comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions · CPC title

• H10D62/343

  Gate regions of field-effect devices having PN junction gates · CPC title