Semiconductor device including vertical wire bonds

Patent metadata

Field	Value
Publication number	US-11749647-B2
Application number	US-202017137990-A
Country	US
Kind code	B2
Filing date	Dec 30, 2020
Priority date	May 22, 2020
Publication date	Sep 5, 2023
Grant date	Sep 5, 2023

Abstract

A semiconductor device includes a vertical column of wire bonds on substrate contact fingers of the device. Semiconductor dies are mounted on a substrate, and electrically coupled to the substrate such that groups of semiconductor dies may have bond wires extending to the same contact finger on the substrate. By bonding those wires to the contact finger in a vertical column, as opposed to separate, side-by-side wire bonds on the contact finger, an area of the contact finger may be reduced.

First claim

We claim:

1. A semiconductor device, comprising:
a substrate, comprising:
a first surface; and
a plurality of contact fingers formed in the first surface; and

a plurality of bond wires, each bond wire having an end with a ball bump, each ball bump of the plurality of bond wires stacked vertically on a contact finger of the plurality of contact fingers;
wherein the contact finger has an area that is smaller than an area required to accommodate two or more bond wires of the plurality of bond wires mounted side-by-side on the contact finger.

2. The semiconductor device of claim 1 , wherein the contact finger is configured to receive between 2 and 6 bond wires.

3. The semiconductor device of claim 1 , further comprising a solder mask applied over the first surface, the solder mask etched to form a window over each of the plurality of contact fingers.

4. The semiconductor device of claim 1 , wherein the contact finger has a length of between 50 μm to 70 μm, and a width of between 50 μm to 70 μm.

5. The semiconductor device of claim 1 , wherein the end of each bond wire further comprises a stitch bond formed at the end of each of the plurality of bond wires.

6. The semiconductor device of claim 1 , wherein the plurality of semiconductor dies comprise between 2 and 6 semiconductor dies.

7. The semiconductor device of claim 1 , wherein the contact finger of the plurality of contact fingers has an area that is less than 28% larger than an area of a ball bump directly affixed to the contact finger.

8. The semiconductor device of claim 1 , wherein each of the plurality of semiconductor dies belongs to a different group of semiconductor dies, each group of semiconductor dies comprising at least two semiconductor dies stacked on each other within the semiconductor device.

9. The semiconductor device of claim 8 , wherein the plurality of semiconductor dies comprise a bottommost semiconductor die in each group of stacked semiconductor dies, a bond wire of the plurality of bond wires extending directly between the bottommost semiconductor die and the contact finger.

10. The semiconductor device of claim 9 , wherein the plurality of semiconductor dies each comprise an edge including die bond pads, the edges of the plurality of semiconductor dies aligned with each other in a reference plane.

11. The semiconductor device of claim 8 , wherein the groups comprise between 2 and 6 groups of semiconductor dies, and the plurality of bond wires bonded to a single contact finger comprise between 2 and 6 bond wires.

12. A semiconductor device, comprising:
a substrate, comprising:
a first surface, and
a plurality of contact fingers formed in the first surface;

at least two groups of semiconductor dies stacked on the first surface, each group comprising one or more semiconductor dies;
a plurality of bond wires extending directly between a semiconductor die from each group of semiconductor dies and the contact fingers, each bond wire having an end with a ball bump, each ball bump of the plurality of bond wires stacked vertically on a contact finger of the plurality of contact fingers;
wherein the contact finger has an area that is smaller than an area required to accommodate two or more bond wires of the plurality of bond wires mounted side-by-side on the contact finger.

13. The semiconductor device of claim 12 , wherein the at least two groups of semiconductor dies comprise between 2 and 6 groups, each group comprising between 2 and 4 semiconductor dies.

14. The semiconductor device of claim 12 , wherein a contact finger of the plurality of contact fingers has a length of between 50 μm to 70 μm, and a width of between 50 μm to 70 μm.

15. The semiconductor device of claim 12 , wherein the contact finger is configured to receive between 2 and 6 bond wires.

16. The semiconductor device of claim 12 , wherein the groups of semiconductor dies comprise between 2 and 6 semiconductor dies.

17. The semiconductor device of claim 12 , wherein the groups of semiconductor dies comprise between 2 and 4 groups of semiconductor dies.

18. The semiconductor device of claim 12 , wherein the contact finger of the plurality of contact fingers has an area that is less than 28% larger than an area of a ball bump directly affixed to the contact finger.

Assignees

• Western Digital Tech Inc

Inventors

• Di Xiaofeng
• Yan Junrong
• Chin Cheekeong
• Wang Weili
• Lu Xin
• Deng Qi
• Ng Chaur Yang
• Zhang Cong
• Yang Chenlin
• Chiu Chin-Tien

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W72/5363

  the connected ends being wedge-shaped · CPC title

• H10W72/536

  the connected ends being ball-shaped · CPC title