Embedded bridge substrate having an integral device

Patent metadata

Field	Value
Publication number	US-11749606-B2
Application number	US-202117371293-A
Country	US
Kind code	B2
Filing date	Jul 9, 2021
Priority date	Jun 20, 2019
Publication date	Sep 5, 2023
Grant date	Sep 5, 2023

Abstract

Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate; a bridge, embedded in the package substrate, wherein the bridge includes an integral passive component, and wherein a surface of the bridge include first contacts in a first interconnect area and second contacts in a second interconnect area; a first die coupled to the passive component via the first contacts in the first interconnect area; and a second die coupled to the second contacts in the second interconnect area.

First claim

The invention claimed is:

1. A microelectronic assembly, comprising:
a substrate having a surface;
a first die on the surface of the substrate;
a second die on the surface of the substrate;
a first interconnect area in the substrate located under the first die;
a second interconnect area in the substrate located under the second die
a bridge, embedded in the substrate under a portion of the first die and a portion of the second die, wherein the bridge includes a bridge substrate and one or more routing layers for signal routing between the first die and the second die, wherein the first interconnect area and the second interconnect area are on the bridge substrate and surround the one or more routing layers; and
a plurality of capacitors located in the first interconnect area and in the second interconnect area, wherein one or more first capacitors of the plurality of capacitors are connected to at least one other capacitor in the plurality of capacitors and one or more second capacitors of the plurality of the capacitors are not connected to another capacitor in the plurality of capacitors, wherein the first die is connected to the one or more first capacitors of the plurality of capacitors.

2. The microelectronic assembly of claim 1 , wherein at least two or more first capacitors of the plurality of capacitors are connected to at least one other capacitor in the plurality of capacitors.

3. The microelectronic assembly of claim 1 , further comprising:
a parasitic resistance connected to the one or more first capacitors of the plurality of capacitors.

4. The microelectronic assembly of claim 1 , further comprising:
a parasitic inductance connected to the one or more first capacitors of the plurality of capacitors.

5. The microelectronic assembly of claim 1 , wherein the plurality of capacitors are part of a power delivery network having a high-frequency current.

6. The microelectronic assembly of claim 1 , wherein the one or more first capacitors of the plurality of capacitors are configured to mitigate electromagnetic interference (EMI) generated by the first die.

7. The microelectronic assembly of claim 1 , wherein the first die is a central processing unit, a graphics processing unit, memory, platform controller hub, memory, a voltage regulator, or an input/output interface.

8. A microelectronic assembly, comprising:
a substrate having a surface;
a first die on the surface of the substrate;
a second die on the surface of the substrate;
a first interconnect area in the substrate located under the first die;
a second interconnect area in the substrate located under the second die;
a bridge, embedded in the substrate under a portion of the first die and a portion of the second die, wherein the bridge includes a bridge substrate and one or more routing layers for signal routing between the first die and the second die, wherein the first interconnect area and the second interconnect area are on the bridge substrate and surround the one or more routing layers; and
a plurality of capacitors located in the first interconnect area and in the second interconnect area, wherein the first die is connected to one or more first capacitors of the plurality of capacitors and is not connected to one or more second capacitors of the plurality of the capacitors.

9. The microelectronic assembly of claim 8 , wherein the first die is connected to two or more first capacitors of the plurality of capacitors.

10. The microelectronic assembly of claim 8 , further comprising:
a parasitic resistance connected to the one or more first capacitors of the plurality of capacitors.

11. The microelectronic assembly of claim 8 , further comprising:
a parasitic inductance connected to the one or more first capacitors of the plurality of capacitors.

12. The microelectronic assembly of claim 8 , wherein the plurality of capacitors are part of a power delivery network having a high-frequency current.

13. The microelectronic assembly of claim 8 , wherein the one or more first capacitors of the plurality of capacitors are configured to mitigate electromagnetic interference (EMI) generated by the first die.

14. The microelectronic assembly of claim 8 , wherein the first die is a central processing unit, a graphics processing unit, memory, platform controller hub, memory, a voltage regulator, or an input/output interface.

15. An integrated circuit (IC) package, comprising:
a package substrate having a surface;
a first die on the surface of the package substrate;
a second die on the surface of the package substrate;
a first bridge interconnect area located under the first die, embedded in the package substrate, having a plurality of capacitors, wherein one or more first capacitors of the plurality of capacitors are connected to at least one other capacitor in the plurality of capacitors and one or more second capacitors of the plurality of the capacitors are not connected to another capacitor in the plurality of capacitors;
a second bridge interconnect area located under the second die, embedded in the package substrate, having a plurality of third capacitors connected to each other; and
a third bridge interconnect area, embedded in the package substrate under a portion of the first die and a portion of the second die and between the first bridge interconnect area and the second bridge interconnect area, wherein the third bridge interconnect area includes conductive pathways for signal routing between the first die and the second dies, wherein the first bridge interconnect area and the second bridge interconnect area surround the third bridge interconnect area.

16. The IC package of claim 15 , further comprising:
a parasitic resistance connected to the one or more first capacitors of the plurality of capacitors.

17. The IC package of claim 15 , further comprising:
a parasitic inductance connected to the one or more first capacitors of the plurality of capacitors.

18. The IC package of claim 15 , wherein the plurality of capacitors are part of a power delivery network having a high-frequency current.

19. The IC package of claim 15 , wherein the one or more first capacitors of the plurality of capacitors are configured to mitigate electromagnetic interference (EMI) generated by the first die.

20. The IC package of claim 15 , wherein the plurality of capacitors are parallel plate capacitors.

Assignees

• Intel Corp

Inventors

• Jain Amit Kumar
• Shekhar Sameer
• Kuan Chin Lee
• Doran Kevin Joseph
• Han Dong-Ho

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title