Data operations and finite state machine for machine learning via bypass of computational tasks based on frequently-used data values

Patent metadata

Field	Value
Publication number	US-11748106-B2
Application number	US-202217683564-A
Country	US
Kind code	B2
Filing date	Mar 1, 2022
Priority date	Apr 9, 2017
Publication date	Sep 5, 2023
Grant date	Sep 5, 2023

Abstract

A mechanism is described for facilitating fast data operations and for facilitating a finite state machine for machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting input data to be used in computational tasks by a computation component of a processor including a graphics processor. The method may further include determining one or more frequently-used data values (FDVs) from the data, and pushing the one or more frequent data values to bypass the computational tasks.

First claim

What is claimed is:

1. An apparatus comprising:
a graphics processor comprising computation circuitry to:
implement a frequently-used data value (FDV) configuration that is to identify a plurality of FDVs, wherein the FDV configuration is to provide a data list consisting of a set of data values defined as FDVs;
apply the FDV configuration to input data received at the computation circuitry, the input data to be used in computational tasks executed by the computation circuitry;
identify, based on the FDV configuration, occurrence in the input data of defined FDVs from the set of data values and of one or more non-FDVs, wherein the one or more non-FDVs consist of other data values that are not comprised in the set of data values;
for the identified FDVs of the input data, cause the identified FDVs to bypass the computational tasks; and
for the one or more non-FDVs of the input data, cause the one or more non-FDVs to be processed by a finite state machine (FSM) implemented by the computation circuitry, wherein the FSM is to:
provide a common primitive for convolution and full connection computation for the computational tasks;
combine memory read accesses; and
merge two or more mathematical operations of the computational tasks.

2. The apparatus of claim 1 , wherein the graphics processor is further to:
set the one or more non-FDVs on a computational path comprising the computational tasks, the computational path to pass through the computation circuitry.

3. The apparatus of claim 2 , wherein the two or more mathematical operations comprise at least one member selected from the group consisting of addition, subtraction, multiplication, or division.

4. The apparatus of claim 1 , wherein the graphics processor is co-located with an application processor on a common semiconductor package.

5. The apparatus of claim 1 , wherein the FSM is further to represent a mathematical model of computation that is an abstract machine.

6. A method comprising:
implementing, by computation circuitry of a graphics processor, a frequently-used data value (FDV) configuration that is to identify a plurality of FDVs, wherein the FDV configuration is to provide a data list consisting of a set of data values defined as FDVs;
applying, by the computation circuitry, the FDV configuration to input data received at the computation circuitry, the input data to be used in computational tasks executed by the computation circuitry;
identifying, by the computation circuitry based on the FDV configuration, occurrence in the input data of defined FDVs from the set of data values and of one or more non-FDVs, wherein the one or more non-FDVs consist of other data values that are not comprised in the set of data values;
for the identified FDVs of the input data, causing, by the computation circuitry, the identified FDVs to bypass the computational tasks; and
for the one or more non-FDVs of the input data, causing, by the computation circuitry, the one or more non-FDVs to be processed by a finite state machine (FSM) implemented by the computation circuitry, wherein the FSM is to:
provide a common primitive for convolution and full connection computation for the computational tasks;
combine memory read accesses; and
merge two or more mathematical operations of the computational tasks.

7. The method of claim 6 , further comprising:
setting the one or more non-FDVs on a computational path comprising the computational tasks, the computational path to pass through the computation circuitry.

8. The method of claim 7 , wherein the two or more mathematical operations comprise at least one member selected from the group consisting of addition, subtraction, multiplication, or division.

9. The method of claim 6 , wherein the graphics processor is co-located with an application processor on a common semiconductor package.

10. The method of claim 6 , wherein the FSM is further to represent a mathematical model of computation that is an abstract machine.

11. A non-transitory machine-readable medium comprising instructions that when executed by a computing device, cause the computing device to perform operations comprising:
implementing, by computation circuitry of a graphics processor, a frequently-used data value (FDV) configuration that is to identify a plurality of FDVs, wherein the FDV configuration is to provide a data list consisting of a set of data values defined as FDVs;
applying, by the computation circuitry, the FDV configuration to input data received at the computation circuitry, the input data to be used in computational tasks executed by the computation circuitry;
identifying, by the computation circuitry based on the FDV configuration, occurrence in the input data of defined FDVs from the set of data values and of one or more non-FDVs, wherein the one or more non-FDVs consist of other data values that are not comprised in the set of data values;
for the identified FDVs of the input data, causing, by the computation circuitry, the identified FDVs to bypass the computational tasks; and
for the one or more non-FDVs of the input data, causing, by the computation circuitry, the one or more non-FDVs to be processed by a finite state machine (FSM) implemented by the computation circuitry, wherein the FSM is to:
provide a common primitive for convolution and full connection computation for the computational tasks;
combine memory read accesses; and
merge two or more mathematical operations of the computational tasks.

12. The non-transitory machine-readable medium of claim 11 , wherein the instructions, when executed by the computing device, further cause the computing device to perform operations comprising:
setting the one or more non-FDVs on a computational path comprising the computational tasks, the computational path to pass through the computing device.

13. The non-transitory machine-readable medium of claim 12 , wherein the two or more mathematical operations comprise at least one member selected from the group consisting of addition, subtraction, multiplication, or division.

14. The non-transitory machine-readable medium of claim 11 , wherein the graphics processor is co-located with an application processor on a common semiconductor package.

15. The non-transitory machine-readable medium of claim 11 , wherein the FSM is further to represent a mathematical model of computation that is an abstract machine.

16. A system comprising:
a memory; and
a graphics processor communicably coupled to the memory, the graphics processor comprising computation circuitry to:
implement a frequently-used data value (FDV) configuration that is to identify a plurality of FDVs, wherein the FDV configuration is to provide a data list consisting of a set of data values defined as FDVs;
apply the FDV configuration to input data received at the computation circuitry, the input data to be used in computational tasks executed by the computation circuitry;
identify, based on the FDV configuration, occurrence in the input data of defined FDVs from the set of data values and of one or more non-FDVs, wherein the one or more non-FDVs consist of other data values that are not comprised in the set of data values;
for the identified FDVs of the input data, cause the identified FDVs to bypass the computational tasks; and
for the one or more non-FDVs of the input data, cause the one or more non-FDVs to be processed by a finite state machine (FSM) implemented by the computation circuitry, wherein the FSM is to:
provide a common primitive for convolution and full connection computation for the computational tasks;
combine memory r

Assignees

• Intel Corp

Inventors

• Ma Liwei
• Satish Nadathur Rajagopalan
• Bottleson Jeremy
• Akhbari Farshad
• Nurvitadhi Eriko
• Appu Abhishek R
• Koker Altug
• Sinha Kamal
• Ray Joydeep
• Vembu Balaji
• Ranganathan Vasanth
• Jahagirdar Sanjeev

Classifications

• G06F9/3832 Primary

  Value prediction for operands; operand history buffers · CPC title

• G06F9/4881 Primary

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title

• G06F9/4498 Primary

  Finite state machines · CPC title

• G06F9/5027

  the resource being a machine, e.g. CPUs, Servers, Terminals · CPC title

• G06F9/544

  Buffers; Shared memory; Pipes · CPC title