Digital LDO regulator for performing asynchronous binary search using binary-weighted PMOS array and operation method thereof

Patent metadata

Field	Value
Publication number	US-11747846-B2
Application number	US-202117465029-A
Country	US
Kind code	B2
Filing date	Sep 2, 2021
Priority date	Mar 29, 2021
Publication date	Sep 5, 2023
Grant date	Sep 5, 2023

Abstract

Disclosed is a digital LDO regulator capable of performing asynchronous binary search using a binary-weighted PMOS array. The digital LDO regulator includes a PMOS array unit including a binary-weighted PMOS array and that binary searches the PMOS array asynchronously, and a mode determining unit that operates in at least one of a fine mode, a coarse mode, and a medium mode, based on an output voltage of the PMOS array unit.

First claim

What is claimed is:

1. A digital LDO regulator comprising:
a PMOS array unit comprising a PMOS array, which is weighted in binary, and configured to asynchronously binary search the PMOS array; and
a mode determining unit configured to operate in at least one of a fine mode, a coarse mode, and a medium mode, based on an output voltage of the PMOS array unit,
wherein the mode determining unit comprises a first operation unit configured to perform the fine mode,
wherein the digital LDO regulator further comprises first to third comparators configured to provide up-down signals to the mode determining unit, and
wherein the first comparator outputs a first up-down signal to the first operation unit based on a first clock signal.

2. The digital LDO regulator of claim 1 , wherein the mode determining unit further comprises
a second operation unit configured to perform at least one of the coarse mode and the medium mode.

3. The digital LDO regulator of claim 2 ,
wherein the second comparator outputs a second up signal to the second operation unit regardless of the first clock signal, and
wherein the third comparator outputs a second down signal to the second operation unit regardless of the clock signal.

4. The digital LDO regulator of claim 1 , wherein the mode determining unit is preset to the fine mode, and
wherein the fine mode is a mode, in which the first comparator connected to a first reference voltage is operated for each clock of the first clock signal.

5. The digital LDO regulator of claim 4 , wherein the fine mode is a mode, in which the output voltage of the PMOS array unit is made close to the first reference voltage.

6. The digital LDO regulator of claim 1 , wherein the mode determining unit performs the coarse mode when it is determined that the output voltage of the PMOS array unit is greater than a second reference high voltage by the second comparator or less than a second reference low voltage by the third comparator.

7. The digital LDO regulator of claim 6 , wherein the coarse mode is a mode that identifies a change in at least one of the second reference high voltage and the second reference low voltage while a second clock signal is input.

8. The digital LDO regulator of claim 6 , wherein, when it is determined that the output of the PMOS array unit is stably set as there is no change in the at least one of the second reference high voltage and the second reference low voltage, an operation performance is changed from the coarse mode to the medium mode.

9. The digital LDO regulator of claim 1 , wherein the medium mode is a mode, in which a PMOS code is determined by identifying whether the output voltage of the PMOS array unit is between which voltages by operating the first comparator.

10. A method of operating a digital LDO regulator including a binary-weighted PMOS array, the method comprising:
performing an asynchronous binary search with respect to the binary-weighted PMOS array; and
controlling an operation in at least one of a fine mode, a coarse mode, and a medium mode, based on an output voltage of the binary-weighted PMOS array,
wherein the controlling of the operation in the at least one of the fine mode, the coarse mode, and the medium mode comprises:
allowing a first comparator connected to a first reference voltage to be operated based on a first clock signal; and
identifying a voltage change of at least one of a second reference high voltage and a second reference low voltage while a second clock signal is input.

11. The method of claim 10 , wherein the controlling of the operation in the at least one of the fine mode, the coarse mode, and the medium mode further comprises
identifying whether the output voltage of the PMOS array is between which voltages by operating the first comparator; and
determining a PMOS code based on the identified voltage.

Assignees

• Univ Korea Res & Bus Found

Inventors

• Kim Chul Woo
• Maeng Jun Young
• Park In Ho
• Jeon Jin Woo
• Kim Hyun Jin

Classifications

• G05F1/563 Primary

  including two stages of regulation at least one of which is output level responsive, e.g. coarse and fine regulation · CPC title

• G05F1/468 Primary

  characterised by reference voltage circuitry, e.g. soft start, remote shutdown · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G05F1/59

  including plural semiconductor devices as final control devices for a single load · CPC title

• G05F1/56

  using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence) · CPC title