Non-linear clamp strength tuning method and apparatus

Patent metadata

Field	Value
Publication number	US-11444532-B2
Application number	US-201916727759-A
Country	US
Kind code	B2
Filing date	Dec 26, 2019
Priority date	Dec 26, 2019
Publication date	Sep 13, 2022
Grant date	Sep 13, 2022

Abstract

A 3-level ripple quantization scheme provides power transistor (MOS) strength-tuning mechanism focused on the transient clamp period. The 3-level ripple quantization scheme solves the digital low dropout's (D-LDO's) tradeoff between silicon area (e.g., decoupling capacitor size), quiescent power consumption (e.g., speed of comparators), wide load range, and optimal output ripple. The 3-level ripple quantization scheme eliminates oscillation risk from either wide dynamic range or parasitic by exploiting asynchronous pulse patterns. As such, ripple magnitude for both fast di/dt loading events and various steady-state scenarios are shrunk effectively, resulting significant efficiency benefits.

First claim

What is claimed is:

1. An apparatus comprising:
a first comparator to compare an output voltage or a divided version of the output voltage on an output power supply rail with a first reference, wherein the first comparator is to generate a first output;
a second comparator to compare the output voltage or a divided version of the output voltage on the output power supply rail with a second reference, wherein the second comparator is to generate a second output;
a third comparator to compare the output voltage or a divided version of the output voltage on the output power supply rail with a third reference, wherein the third comparator is to generate a third output;
power gates coupled to the output power supply rail;
a first controller to receive the first and second outputs and to generate a code indicative of a coarse setting for power gates; and
a second controller to receive the first, second, and third outputs, wherein the second controller is to generate a fine code for the power gates;
wherein the first reference has a voltage level below a voltage level of the second reference, and wherein the third reference has a voltage level below the voltage level of the first reference.

2. The apparatus of claim 1 , further comprising a gating logic to receive the coarse and fine codes, and to generate a two dimensional code to enable power gates, wherein the power gates are arranged in an array configuration.

3. The apparatus of claim 2 , wherein the array configuration is a thermometer array.

4. The apparatus of claim 2 , wherein the array configuration is a binary array.

5. The apparatus of claim 1 , wherein the first output when asserted indicates that the output voltage is below the first reference, wherein the second output when asserted indicates that the output voltage is above the second threshold, and wherein the third output when asserted indicates that the output voltage is below the third reference.

6. The apparatus of claim 1 , wherein the second controller provides non-linear strength tuning of the power gates, wherein the first controller provides linear strength tuning of the power gates.

7. The apparatus of claim 1 , wherein the second controller comprises a pattern detector, which generates a pulse when the first and second outputs appear in a staggered order indicative of an oscillation of the output voltage.

8. The apparatus of claim 7 , wherein the second controller further comprises a filter coupled to an output of the pattern detector to filter the pulse from noise.

9. The apparatus of claim 8 , wherein the second controller further comprises a shift register coupled to the output of the filter, wherein the shift register generates the fine code dynamically.

10. An apparatus comprising:
a first comparator to compare an output voltage or a divided version of the output voltage on an output power supply rail with a first reference, wherein the first comparator is to generate a first output;
a second comparator to compare the output voltage or a divided version of the output voltage on the output power supply rail with a second reference, wherein the second comparator is to generate a second output;
a third comparator to compare the output voltage or a divided version of the output voltage on the output power supply rail with a third reference, wherein the third comparator is to generate a third output;
power gates coupled to the output power supply rail;
a first controller to receive the first and second outputs and to generate a first code for linear strength tuning of the power gates; and
a second controller to receive the first, second, and third outputs, wherein the second controller is to generate a second code for non-linear strength tuning of the power gates, and wherein the second controller comprises a pattern detector that generates a pulse when the first and second outputs appear in a staggered order indicative of an oscillation of the output voltage.

11. The apparatus of claim 10 , wherein the second controller further comprises a filter coupled to an output of the pattern detector to filter the pulse from noise.

12. The apparatus of claim 11 , wherein the second controller further comprises a shift register coupled to the output of the filter, wherein the shift register generates the non-linear code dynamically.

13. A system comprising:
a memory;
a processor core coupled to the memory;
a digital low dropout (D-LDO) regulator to receive an input power supply voltage and to generate an output power supply voltage on an output power supply rail for the processor core, wherein the D-LDO comprises:
a 3-level ripple quantization circuitry to generate first, second, and third outputs in accordance with first, second, and third reference voltages, respectively;
power gates coupled to the output power supply rail;
a first controller to receive the first and second outputs and to generate a first code for linear strength tuning of the power gates; and
a second controller to receive the first, second, and third outputs, wherein the second controller is to generate a second code for non-linear strength tuning of the power gates, and wherein the second controller comprises a pattern detector which generates a pulse when the first and second outputs appear in a staggered order indicative of an oscillation of the output voltage; and

a wireless interface to allow the processor to communicate with another device.

14. The system of claim 13 , wherein the second controller further comprises a filter coupled to an output of the pattern detector to filter the pulse from noise.

15. The system of claim 14 , wherein the second controller further comprises a shift register coupled to the output of the filter, wherein the shift register generates the non-linear code dynamically.

16. The system of claim 13 , wherein the D-LDO comprises a gating logic to receive the linear and non-linear codes, and to generate a two dimensional code to enable power gates, wherein the power gates are arranged in an array configuration.

17. The system of claim 16 , wherein the array configuration is one of a thermometer array or a binary array.

18. An apparatus comprising:
a first comparator to compare an output voltage or a divided version of the output voltage on an output power supply rail with a first reference, wherein the first comparator is to generate a first output;
a second comparator to compare the output voltage or a divided version of the output voltage on the output power supply rail with a second reference, wherein the second comparator is to generate a second output;
a third comparator to compare the output voltage or a divided version of the output voltage on the output power supply rail with a third reference, wherein the third comparator is to generate a third output;
power gates coupled to the output power supply rail;
a first controller to receive the first and second outputs and to generate a code indicative of a coarse setting for power gates; and
a second controller to receive the first, second, and third outputs, wherein the second controller is to generate a fine code for the power gates, and wherein the second controller comprises a pattern detector, which generates a pulse when the first and second outputs appear in a staggered order indicative of an oscillation of the output voltage.

19. The apparatus of claim 18 , wherein the second controller comprises a filter coupled to an output of the pattern detector to filter the pulse from noise.

20. The apparatus of claim 19 , wher

Assignees

• Intel Corp

Inventors

• Liu Xiaosen
• Ravichandran Krishnan
• Krishnamurthy Harish
• De Vivek

Classifications

• H02M3/158 Primary

  including plural semiconductor devices as final control devices for a single load · CPC title

• H02M3/073

  Charge pumps of the Schenkel-type · CPC title

• G05F1/571

  with overvoltage detector · CPC title

• H02M1/088 Primary

  for the simultaneous control of series or parallel connected semiconductor devices · CPC title

• G05F1/59

  including plural semiconductor devices as final control devices for a single load · CPC title