Semiconductor device

Patent metadata

Field	Value
Publication number	US-11742427-B2
Application number	US-202217677791-A
Country	US
Kind code	B2
Filing date	Feb 22, 2022
Priority date	Feb 25, 2019
Publication date	Aug 29, 2023
Grant date	Aug 29, 2023

Abstract

The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, having a plurality of fins on a surface of the substrate; a gate structure across the plurality of fins. The gate structure is located on a portion of a top surface and sidewall surfaces of the plurality of fins. The gate structure includes a first region and a second region on the first region. A bottom boundary of the second region is higher than the top surface of the plurality of fins. A size of the first region in an extending direction of the plurality of fins is smaller than a size of the second region in the extending direction of the plurality of fins.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate, having a plurality of fins on a surface of the substrate;
a gate structure across the plurality of fins; and
a mask protection layer on the top surface of the plurality of fins, the mask protection layer being made of one of silicon oxide, silicon nitride, and silicon oxynitride;
wherein:
the gate structure is located on a portion of a top surface and sidewall surfaces of the plurality of fins;
the gate structure includes a first region and a second region on the first region;
a bottom boundary of the second region is higher than the top surface of the plurality of fins;
a size of the first region in an extending direction of the plurality of fins is smaller than a size of the second region in the extending direction of the plurality of fins; and
an interface plane between the first region and the second region is coplanar with a top surface of the mask protection layer.

2. The device according to claim 1 , wherein:
the first region of the gate structure has an inverted trapezoid in a cross section parallel to the extending direction of the plurality of fins and perpendicular to a surface of the substrate.

3. The device according to claim 1 , wherein:
the gate structure includes: a gate dielectric layer, and a gate electrode layer on the gate dielectric layer; and
the gate electrode layer is made of one of polysilicon and polycrystalline germanium.

4. The device according to claim 1 , further comprising:
an isolation structure on the surface of the substrate, wherein the isolation structure covers a portion of sidewalls of the plurality of fins, a top surface of the isolation structure is lower than the top surface of the plurality of fins, and the gate structure is located on a portion of a surface of the isolation structure.

5. The device according to claim 1 , further comprising:
source-drain doped regions in the plurality of fins on both sides of the gate structure.

6. The device according to claim 1 , wherein:
the first region of the gate structure has a reverse trapezoid profile.

7. The device according to claim 1 , further including:
a mask layer formed on the gate structure.

Assignees

• Semiconductor Mfg Int Shanghai Corp
• Semiconductor Mfg Int Beijing Corp

Inventors

• Zhang Haiyang
• Su Bo

Classifications

• H10P50/268

  of silicon-containing layers · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10P50/267

  using plasmas · CPC title

• H10P50/73

  using masks for insulating materials · CPC title