Electronic device with gallium nitride transistors and method of making same

Patent metadata

Field	Value
Publication number	US-11742390-B2
Application number	US-202017085558-A
Country	US
Kind code	B2
Filing date	Oct 30, 2020
Priority date	Oct 30, 2020
Publication date	Aug 29, 2023
Grant date	Aug 29, 2023

Abstract

Fabrication methods and gallium nitride transistors, in which an electronic device includes a substrate, a buffer structure, a hetero-epitaxy structure over the buffer structure, and a transistor over or in the hetero-epitaxy structure. In one example, the buffer structure has an extrinsically carbon doped gallium nitride layer over a dual superlattice stack or over a multilayer composition graded aluminum gallium nitride stack, and a silicon nitride cap layer over the hetero-epitaxy structure.

First claim

What is claimed is:

1. An electronic device, comprising:
a substrate;
a buffer structure over the substrate;
a hetero-epitaxy structure over the buffer structure; and
a transistor having a gate over the hetero-epitaxy structure, a drain partially in the hetero-epitaxy structure and spaced apart from the gate, and a source partially in the hetero-epitaxy structure and spaced apart from the gate and from the drain;
the buffer structure having a dual superlattice stack that comprises:
a first superlattice over an aluminum nitride layer of the buffer structure, the first superlattice having alternating pairs of respective aluminum nitride and aluminum gallium nitride sublayers;
an aluminum gallium nitride interlayer over the first superlattice; and
a second superlattice over the aluminum gallium nitride interlayer, the second superlattice having alternating pairs of respective aluminum nitride and gallium nitride sublayers.

2. The electronic device of claim 1 , further comprising a silicon nitride cap layer over the hetero-epitaxy structure.

3. The electronic device of claim 2 , wherein the silicon nitride cap layer has a thickness of 2-10 nm.

4. The electronic device of claim 1 , wherein the transistor is an enhancement mode transistor, the electronic device further comprising a p-doped gallium nitride layer spaced apart from the source and from the drain over the hetero-epitaxy structure, the gate being over the p-doped gallium nitride layer.

5. The electronic device of claim 1 , wherein the transistor is a depletion mode transistor, the gate being over the hetero-epitaxy structure.

6. The electronic device of claim 1 , wherein:
the aluminum nitride sublayers of the first superlattice have respective thicknesses of 10-20 nm; and
the aluminum gallium nitride sublayers of the first superlattice have respective thicknesses of 15-35 nm, and an aluminum concentration of 60-80%.

7. The electronic device of claim 6 , wherein:
the aluminum nitride sublayers of the second superlattice have respective thicknesses of 10-25 nm; and
the gallium nitride sublayers of the second superlattice have respective thicknesses of 15-35 nm.

8. The electronic device of claim 7 , wherein the aluminum gallium nitride interlayer has a thickness of 10-100 nm, and an aluminum concentration of 40-60%.

9. The electronic device of claim 1 , wherein:
the aluminum nitride sublayers of the second superlattice have respective thicknesses of 10-25 nm; and
the gallium nitride sublayers of the second superlattice have respective thicknesses of 15-35 nm.

10. The electronic device of claim 1 , wherein the aluminum gallium nitride interlayer has a thickness of 10-100 nm, and an aluminum concentration of 40-60%.

11. A method of fabricating an electronic device, the method comprising:
forming a buffer structure over a substrate, including:
forming an aluminum nitride layer over the substrate; and
performing an epitaxial deposition process that deposits at least one layer of the buffer structure using an extrinsic carbon source gas;

forming a hetero-epitaxy structure over the buffer structure, the hetero-epitaxy structure including an aluminum nitride layer over the buffer structure and an aluminum gallium nitride layer over the aluminum nitride layer; and
forming a transistor having a gate over the hetero-epitaxy structure, a drain extended partially into the aluminum gallium nitride layer of the hetero-epitaxy structure and spaced apart from the gate, and a source extended partially into the aluminum gallium nitride layer of the hetero-epitaxy structure and spaced apart from the gate and from the drain.

12. The method of claim 11 , wherein forming the buffer structure comprises:
performing a first epitaxial deposition process that forms a first superlattice over the aluminum nitride layer, the first superlattice having alternating pairs of aluminum nitride sublayers and aluminum gallium nitride sublayers;
performing a second epitaxial deposition process that forms an aluminum gallium nitride interlayer over the first superlattice; and
performing a third epitaxial deposition process that forms a second superlattice over the aluminum gallium nitride interlayer, the second superlattice having alternating pairs of aluminum nitride sublayers and gallium nitride sublayers.

13. The method of claim 11 , further comprising:
performing a metal organic chemical vapor deposition process that forms a silicon nitride cap layer over the hetero-epitaxy structure.

14. The method of claim 11 , wherein the extrinsic carbon source gas includes ethene or hexene.

15. A method of fabricating an electronic device, the method comprising:
forming a buffer structure over a substrate, including:
forming an aluminum nitride layer over the substrate; and
performing an epitaxial deposition process that deposits at least one layer of the buffer structure using an extrinsic carbon source gas;

forming a hetero-epitaxy structure over the buffer structure;
forming a transistor having a gate over the hetero-epitaxy structure, a drain partially in the hetero-epitaxy structure and spaced apart from the gate, and a source partially in the hetero-epitaxy structure and spaced apart from the gate and from the drain, wherein forming the buffer structure comprises:
performing a first epitaxial deposition process that forms a first aluminum gallium nitride sublayer over the aluminum nitride layer;
performing a second epitaxial deposition process that forms a second aluminum gallium nitride sublayer over the first aluminum gallium nitride sublayer using the extrinsic carbon source gas; and
performing a third epitaxial deposition process that forms a third aluminum gallium nitride sublayer over the second aluminum gallium nitride sublayer using the extrinsic carbon source gas.

16. The method of claim 15 , further comprising:
performing a metal organic chemical vapor deposition process that forms a silicon nitride cap layer over the hetero-epitaxy structure.

17. A method of fabricating an electronic device, the method comprising:
forming a buffer structure over a substrate, including:
forming an aluminum nitride layer over the substrate;
performing a first epitaxial deposition process that forms a first superlattice over the aluminum nitride layer, the first superlattice having alternating pairs of aluminum nitride sublayers and aluminum gallium nitride sublayers;
performing a second epitaxial deposition process that forms an aluminum gallium nitride interlayer over the first superlattice; and
performing a third epitaxial deposition process that forms a second superlattice over the aluminum gallium nitride interlayer, the second superlattice having alternating pairs of aluminum nitride sublayers and gallium nitride sublayers;

forming a hetero-epitaxy structure over the buffer structure; and
forming a transistor having a gate over the hetero-epitaxy structure, a drain partially in the hetero-epitaxy structure and spaced apart from the gate, and a source partially in the hetero-epitaxy structure and spaced apart from the gate and from the drain.

18. The method of claim 17 , wherein forming the buffer structure further comprises performing an epitaxial deposition process that deposits at least one layer of the buffer structure using an extrinsic carbon source gas.

19. The method of claim 18 , wherein the extrinsic carbon source gas is or includes ethene.

20. The method of claim 17 , further comprising:
performing a metal organic chemical vapor depositi

Assignees

• Texas Instruments Inc

Inventors

• Fareed Qhalid R S
• Lee Dong Seup
• Dellas Nicholas S

Classifications

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3252

  Alternating layers, e.g. superlattice · CPC title

• H10P14/3216 Primary

  Nitrides · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10P14/3416

  Nitrides · CPC title