Gallium nitride devices including a tunnel barrier layer

Patent metadata

Field	Value
Publication number	US-2020203520-A1
Application number	US-201816228364-A
Country	US
Kind code	A1
Filing date	Dec 20, 2018
Priority date	Dec 20, 2018
Publication date	Jun 25, 2020
Grant date	—

Abstract

In some examples, a gallium-based device comprises a substrate layer; a first group-III nitride layer supported by the substrate layer; a second group-III nitride layer supported by the first group-III nitride layer; a tunnel barrier layer supported by the second group-III nitride layer; a passivation layer supported by the tunnel barrier layer; and source, gate, and drain contact structures supported by the first group-III nitride layer.

First claim

What is claimed is:

1 . A gallium-based device, comprising:
a substrate layer; a first group-III nitride layer supported by the substrate layer; a second group-III nitride layer supported by the first group-III nitride layer; a tunnel barrier layer supported by the second group-III nitride layer; a passivation layer supported by the tunnel barrier layer; and source, gate, and drain contact structures supported by the first group-III nitride layer.

2 . The gallium-based device of claim 1 , wherein the substrate layer includes silicon.

3 . The gallium-based device of claim 2 , wherein a seed layer is positioned between the substrate layer and the first group-III nitride layer.

4 . The gallium-based device of claim 1 , wherein at least a portion of the first group-III nitride layer has a chemical composition of Al(0)Ga(1)N.

5 . The gallium-based device of claim 1 , wherein the second group-III nitride layer has a chemical composition of Al(X)In(Y)Ga(1-X-Y)N, wherein X and Y are concentrations of aluminum (Al) and Indium (In), respectively, and 1-X-Y is the concentration of gallium (Ga).

6 . The gallium-based device of claim 1 , wherein the tunnel barrier layer includes aluminum nitride (AlN).

7 . The gallium-based device of claim 1 , wherein the tunnel barrier layer has a chemical composition of Al(X)In(Y)Ga(1-X-Y)N, wherein X and Y are concentrations of aluminum and Indium, respectively, and 1-X-Y is the concentration of gallium (Ga).

8 . A method of fabricating a gallium-based device, comprising:
obtaining a substrate; growing a first group-III nitride layer that is supported by the substrate; growing a second group-III nitride layer that is supported by the first group-III nitride layer; growing a tunnel barrier layer that is supported by the second group-III nitride layer; growing a passivation layer that is supported by the tunnel barrier layer; and depositing source, gate, and drain contact structures that are supported by the second group-III nitride layer.

9 . The method of claim 8 , wherein the substrate includes silicon.

10 . The method of claim 8 , wherein the at least a portion of the first group-III nitride layer has a chemical composition of Al(0)Ga(1)N.

11 . The method of claim 8 , wherein the second group-III nitride layer has a chemical composition of Al(X)In(Y)Ga(1-X-Y)N, where X, Y are concentrations of aluminum and Indium, respectively, and 1-X-Y is the concentration of gallium (Ga).

12 . The method of claim 8 , wherein the tunnel barrier layer includes aluminum nitride (AlN).

13 . The method of claim 8 , wherein the tunnel barrier layer has a chemical composition of Al(X)In(Y)Ga(1-X-Y)N, where X, Y are concentrations of aluminum and Indium, respectively, and 1-X-Y is the concentration of gallium (Ga).

14 . A gallium-based transistor, comprising:
a substrate including silicon; a seed layer positioned on the silicon substrate; a gallium nitride layer positioned on the seed layer; an aluminum gallium nitride layer positioned on the gallium nitride layer, wherein a two-dimensional electron gas (2DEG) is at an interface of the aluminum gallium nitride layer and the gallium nitride layer; an aluminum nitride layer positioned on the aluminum gallium nitride layer; a passivation layer positioned on the aluminum nitride layer; and source, drain, and gate contact structures supported by the aluminum gallium nitride layer.

15 . The gallium-based transistor of claim 14 , wherein the aluminum nitride layer is configured to prevent electrons from the 2DEG to tunnel to the passivation layer.

16 . The gallium-based transistor of claim 14 , wherein the seed layer includes aluminum nitride.

17 . The gallium-based transistor of claim 14 , wherein at least a portion of the gallium nitride layer has a chemical composition of Al(0)Ga(1)N.

18 . The gallium-based transistor of claim 14 , wherein at least another portion of the gallium nitride layer has a chemical composition of Al(X)In(Y)Ga(1-X-Y)N, where X, Y are the concentrations of aluminum and indium, respectively, and 1-X-Y is the concentration of gallium (Ga).

19 . The gallium-based transistor of claim 14 , wherein the aluminum gallium nitride layer has a chemical composition of Al(X)In(Y)Ga(1-X-Y)N, where X, Y are concentrations of aluminum and Indium, respectively, and 1-X-Y is the concentration of gallium (Ga).

20 . The gallium-based transistor of claim 14 , wherein the passivation layer includes silicon dioxide.

Assignees

• Texas Instruments Inc

Inventors

• Dellas Nicholas S
• Rangoon Sayeed Qhalid Fareed

Classifications

• H10P14/3416

  Nitrides · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10P14/3216

  Nitrides · CPC title

• H10P14/3248

  consisting of two layers · CPC title