Semiconductor device and semicondutor devce examination method
US-2023079823-A1 · Mar 16, 2023 · US
Semiconductor device and semiconductor device examination method
US11740287B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11740287-B2 |
| Application number | US-202217690443-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 9, 2022 |
| Priority date | Sep 10, 2021 |
| Publication date | Aug 29, 2023 |
| Grant date | Aug 29, 2023 |
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- Title
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- Abstract
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- Assignees and inventors
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- First independent claim
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Abstract
Official abstract text for this publication.
A semiconductor device of the embodiment includes a plurality of scan chains, a shift clock control circuit, and a shift clock generation circuit. The plurality of scan chains each include a plurality of scan flip-flops. The shift clock control circuit outputs, to each of the plurality of scan chains, a control signal that non-inverts or inverts a scan clock signal. The shift clock generation circuit is provided to each of the plurality of scan flip-flops and generates a non-inverted scan clock signal or an inverted scan clock signal based on the control signal, the non-inverted scan clock signal being obtained by non-inverting the scan clock signal, the inverted scan clock signal being obtained by inverting the scan clock signal.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor device comprising: a plurality of scan chains each including a plurality of scan flip-flops; a shift clock control circuit configured to output, to each of the plurality of scan chains, a control signal that non-inverts or inverts a scan clock signal; and a shift clock generation circuit provided to each of the plurality of scan flip-flops and configured to generate a non-inverted scan clock signal or an inverted scan clock signal based on the control signal, the non-inverted scan clock signal being obtained by non-inverting the scan clock signal, the inverted scan clock signal being obtained by inverting the scan clock signal. 2. The semiconductor device according to claim 1 , wherein the shift clock control circuit is configured to generate the control signal so that a ratio of scan chains that perform shift operation in accordance with the non-inverted scan clock signal among the plurality of scan chains is substantially equal to a ratio of scan chains that perform shift operation in accordance with the inverted scan clock signal among the plurality of scan chains. 3. The semiconductor device according to claim 1 , wherein the shift clock control circuit is configured to generate the control signal so that a ratio of scan flip-flops that perform shift operation in accordance with the non-inverted scan clock signal among the plurality of scan flip-flops is substantially equal to a ratio of scan flip-flops that perform shift operation in accordance with the inverted scan clock signal among the plurality of scan flip-flops. 4. The semiconductor device according to claim 1 , wherein the shift clock generation circuit includes a logical conjunction circuit configured to calculate logical conjunction of the control signal and a test enable signal and an exclusive disjunction circuit configured to calculate exclusive disjunction of an output signal from the logical conjunction circuit and the scan clock signal. 5. A semiconductor device examination method of examining a semiconductor device including a plurality of scan chains each including a plurality of scan flip-flops, the method comprising: outputting, to each of the plurality of scan chains, a control signal that non-inverts or inverts a scan clock signal; generating a non-inverted scan clock signal or an inverted scan clock signal based on the control signal, the non-inverted scan clock signal being obtained by non-inverting the scan clock signal, the inverted scan clock signal being obtained by inverting the scan clock signal; and performing scan shift operation in accordance with the non-inverted scan clock signal or the inverted scan clock signal. 6. The semiconductor device examination method according to claim 5 , further comprising: generating the control signal so that a ratio of scan chains that perform shift operation in accordance with the non-inverted scan clock signal among the plurality of scan chains is substantially equal to a ratio of scan chains that perform shift operation in accordance with the inverted scan clock signal among the plurality of scan chains. 7. The semiconductor device examination method according to claim 5 , further comprising: generating the control signal so that a ratio of scan flip-flops that perform shift operation in accordance with the non-inverted scan clock signal among the plurality of scan flip-flops is substantially equal to a ratio of scan flip-flops that perform shift operation in accordance with the inverted scan clock signal among the plurality of scan flip-flops.
Assignees
Inventors
Classifications
- G01R31/318536Primary
Scan chain arrangements, e.g. connections, test bus, analog signals · CPC title
Scan latches or cell details · CPC title
- G01R31/318552Primary
Clock circuits details · CPC title
Control logic · CPC title
Multiple simultaneous testing of subparts · CPC title
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Frequently asked questions
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- What does patent US11740287B2 cover?
- A semiconductor device of the embodiment includes a plurality of scan chains, a shift clock control circuit, and a shift clock generation circuit. The plurality of scan chains each include a plurality of scan flip-flops. The shift clock control circuit outputs, to each of the plurality of scan chains, a control signal that non-inverts or inverts a scan clock signal. The shift clock generation c…
- Who is the assignee on this patent?
- Kioxia Corp
- What technology area does this patent fall under?
- Primary CPC classification G01R31/318536. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Aug 29 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).