Signal processing circuit, corresponding sensor device and apparatus

Patent metadata

Field	Value
Publication number	US-11740136-B2
Application number	US-202017011723-A
Country	US
Kind code	B2
Filing date	Sep 3, 2020
Priority date	Apr 27, 2017
Publication date	Aug 29, 2023
Grant date	Aug 29, 2023

Abstract

A circuit includes a first input terminal, a second input terminal, a third input terminal and an output terminal. A first summation node adds signals at the first and third input terminals. A second summation node subtracts signals at the second and third input terminals. A selector selects between the added signals and subtracted signals in response to a selection signal. The output of the selector is integrated to generate an integrated signal. The integrated signal is compared by a comparator to a threshold, the comparator generating an output signal at the output terminal having a first level and a second level. Feedback of the output signal produces the selection signal causing the selector to select the added signals in response to the first level of the output signal and causing the selector to select the subtracted signals in response to the second level of the output signal.

First claim

The invention claimed is:

1. A method, comprising:
additively combining a first signal and a third signal to generate an addition signal;
subtractively combining a second signal and the third signal to generate a subtraction signal;
selecting the addition signal for output as a selection signal in response to a first logic state of a bit in a selection bitstream;
selecting the subtraction signal for output as said selection signal in response to a second logic state of the bit in the selection bitstream;
integrating the selection signal to generate an integration signal; and
comparing the integration signal to a threshold to generate each bit of the selection bitstream.

2. The method of claim 1 , further comprising maintaining the third signal at a level lower than a level of said second signal.

3. The method of claim 1 , wherein an average value of said selection bitstream lies between 0 and 1.

4. The method of claim 3 , further comprising displaying an average value generated by digitally decimating the selection bitstream.

5. The method of claim 4 , wherein said third signal is generated by a temperature sensor, and wherein said displaying comprises displaying a temperature value.

6. The method of claim 1 , further comprising digitally decimating the selection bitstream.

7. The method of claim 1 , wherein said first signal is a proportional to absolute temperature signal and said second signal is a complementary to absolute temperature signal and said third signal is generated by a temperature sensor.

8. The method of claim 7 , wherein said temperature sensor is a thermopile.

9. The method of claim 7 , further comprising:
generating said proportional to absolute temperature signal by determining a difference in base-to-emitter voltages of two bipolar transistors; and
generating said complementary to absolute temperature signal by determining a base-to-emitter voltage of a further bipolar transistor.

10. The method of claim 1 , further comprising generating bits of the selection bitstream at a rate corresponding to a sampling rate for comparing the integration signal to the threshold.

11. The method of claim 1 , wherein each of the first signal, second signal, third signal, addition signal, subtraction signal, selection signal, and integration signal is an analog signal.

12. The method of claim 1 , wherein:
selecting the addition signal for output as the selection signal comprises controlling a multiplexer circuit having the addition signal as an input to pass the addition signal in response to the first logic state of the bit in the selection bitstream; and
selecting the subtraction signal for output as the selection signal comprises controlling the multiplexer circuit having the subtraction signal as an input to pass the subtraction signal in response to the second logic state of the bit in the selection bitstream.

Assignees

• St Microelectronics Srl

Inventors

• Vaiana Michele
• Pesenti Paolo
• Chiricosta Mario
• Ippolito Calogero Marco
• Maiore Mario

Classifications

• G01K3/14 Primary

  in respect of space · CPC title

• G01K7/02 Primary

  using thermoelectric elements, e.g. thermocouples · CPC title

• G01K7/021

  Particular circuit arrangements (G01K7/026, G01K7/12, G01K7/14 take precedence) · CPC title

• H03H17/02

  Frequency selective networks {(digital computers for complex mathematical operations G06F17/10)} · CPC title

• G01K2219/00

  Thermometers with dedicated analog to digital converters · CPC title