Signal processing circuit, corresponding sensor device and apparatus

Patent metadata

Field	Value
Publication number	US-10794772-B2
Application number	US-201815957999-A
Country	US
Kind code	B2
Filing date	Apr 20, 2018
Priority date	Apr 27, 2017
Publication date	Oct 6, 2020
Grant date	Oct 6, 2020

Abstract

A circuit includes a first input terminal, a second input terminal, a third input terminal and an output terminal. A first summation node adds signals at the first and third input terminals. A second summation node subtracts signals at the second and third input terminals. A selector selects between the added signals and subtracted signals in response to a selection signal. The output of the selector is integrated to generate an integrated signal. The integrated signal is compared by a comparator to a threshold, the comparator generating an output signal at the output terminal having a first level and a second level. Feedback of the output signal produces the selection signal causing the selector to select the added signals in response to the first level of the output signal and causing the selector to select the subtracted signals in response to the second level of the output signal.

First claim

The invention claimed is:

1. A circuit, comprising:
a first input terminal, a second input terminal, a third input terminal and an output terminal,
a first summation node configured to additively combine signals received from the first input terminal and the third input terminal,
a second summation node configured to subtractively combine signals received from the third input terminal and the second input terminal,
a selector having a first input coupled to receive a signal output from the first summation node, a second input coupled receive a signal output from the second summation node and an output that is selectively coupled to the first input or the second input in response to a selection signal,
an integrator configured to integrate a signal output from the selector output to generate an integrated signal at an integrator output,
a comparator configured to compare the integrated signal to a threshold and generate at the output terminal an output signal having a first level and a second level, and
a feedback line coupling the output signal to the selector as the selection signal such that the selector selectively couples to the first input in response to the first level of the output signal and selectively couples to the second input in response to the second level of the output signal.

2. The circuit of claim 1 , wherein the first and second levels of said output signal are binary levels.

3. The circuit of claim 2 , further including an averaging circuit configured to produce an average value of the binary levels of said output signal.

4. The circuit of claim 3 , wherein the averaging circuit includes a decimation filter configured to filter said output signal.

5. The circuit of claim 3 , further comprising a display configured to display the average value.

6. A circuit, comprising:
a first input terminal, a second input terminal, a third input terminal and an output terminal,
a first summation node configured to additively combine signals from the first input terminal and the third input terminal,
a second summation node configured to subtractively combine signals from the third input terminal and the second input terminal,
a selector having a first input coupled to an output of the first summation node, a second input coupled to an output of the second summation node and an output that is selectively coupled to the first input or the second input in response to a selection signal,
an integrator configured to integrate a signal output from the selector output to generate an integrated signal at an integrator output,
a comparator configured to compare the integrated signal to a threshold and generate at the output terminal an output signal having a first level and a second level,
a feedback line coupling the output signal to the selector as the selection signal such that the selector selectively couples to the first input in response to the first level of the output signal and selectively couples to the second input in response to the second level of the output signal;
a proportional to absolute temperature (PTAT) sensor configured to generate a PTAT signal at the first input terminal;
a complementary to absolute temperature (CTAT) sensor configured to generate a CTAT signal at the second input terminal; and
a thermopile configured to generate a temperature difference signal at the third input terminal.

7. The circuit of claim 6 , wherein an average value of said output signal is indicative of a temperature of an object sensed by said thermopile.

8. The circuit of claim 7 , further including an averaging circuit configured to produce said average value.

9. The circuit of claim 8 , wherein the averaging circuit includes a decimation filter configured to filter said output signal.

10. The circuit of claim 6 , wherein the PTAT sensor includes a pair of bipolar transistors differing from each other for at least one of the transistor area and transistor bias current, wherein the PTAT signal includes the difference of the base-to-emitter voltages of the bipolar transistors in said pair of bipolar transistors.

11. The circuit of claim 6 , wherein the CTAT sensor includes a single bipolar transistor, wherein the CTAT signal includes the base-to-emitter voltage of said single bipolar transistor.

12. The circuit of claim 6 , further including an averaging circuit configured to produce an average value of said output signal.

13. The circuit of claim 12 , wherein the averaging circuit includes a decimation filter configured to filter said output signal.

14. The circuit of claim 6 , wherein the first and second levels of said output signal are binary levels.

15. The circuit of claim 14 , further including an averaging circuit configured to produce an average value of the binary levels of said output signal.

16. The circuit of claim 15 , wherein the averaging circuit includes a decimation filter configured to filter said output signal.

17. The circuit of claim 15 , further comprising a display configured to display the average value.

18. A circuit, comprising:
a first input terminal, a second input terminal, a third input terminal and an output terminal,
a first summation node configured to additively combine signals from the first input terminal and the third input terminal,
a second summation node configured to subtractively combine signals from the third input terminal and the second input terminal,
a selector having a first input coupled to an output of the first summation node, a second input coupled to an output of the second summation node and an output that is selectively coupled to the first input or the second input in response to a selection signal,
an integrator configured to integrate a signal output from the selector output to generate an integrated signal at an integrator output,
a comparator configured to compare the integrated signal to a threshold and generate at the output terminal an output signal having a first level and a second level,
a feedback line coupling the output signal to the selector as the selection signal such that the selector selectively couples to the first input in response to the first level of the output signal and selectively couples to the second input in response to the second level of the output signal;
a first sensor providing a signal at the first input terminal that increases with increase in a first sensed condition;
a second sensor providing a signal at the second input terminal that decreases with increase in the first sensed condition,
a third sensor providing a signal at the third input terminal indicative of a difference between a second sensed condition and the first sensed condition.

19. The circuit of claim 18 , wherein the first sensed condition is ambient temperature and the second sensed condition is temperature of an object, wherein an average value of said output signal is indicative of the temperature of said object.

20. The circuit of claim 18 , further including an averaging circuit configured to produce an average value of said output signal.

21. The circuit of claim 20 , wherein the averaging circuit block includes a decimation filter configured to filter said output signal.

22. The circuit of claim 18 , wherein the first and second levels of said output signal are binary levels.

23. The circuit of claim 22 , further including an averaging circuit configured to produce an average value of the binary levels of said output signal.

24. The circuit of cl

Assignees

• St Microelectronics Srl

Inventors

• Vaiana Michele
• Pesenti Paolo
• Chiricosta Mario
• Ippolito Calogero Marco
• Maiore Mario

Classifications

• H03K19/01825

  Coupling arrangements, impedance matching circuits · CPC title

• H03K19/00307 Primary

  in bipolar transistor circuits · CPC title

• G01K2219/00

  Thermometers with dedicated analog to digital converters · CPC title

• G01K7/02 Primary

  using thermoelectric elements, e.g. thermocouples · CPC title

• H03M3/456

  the modulator having a first order loop filter in the feedforward path · CPC title