Display device using semiconductor light emitting device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-11735701-B2
Application number	US-202117153592-A
Country	US
Kind code	B2
Filing date	Jan 20, 2021
Priority date	Feb 25, 2020
Publication date	Aug 22, 2023
Grant date	Aug 22, 2023

Abstract

Discussed are a display device and a method of manufacturing the same, and more particularly, to a display device including a semiconductor light emitting device having a size of several μm to several tens of μm and a method of manufacturing the same. The present disclosure provides a display device, including a base portion, a plurality of transistors disposed on the base portion, a plurality of semiconductor light emitting devices disposed on the base portion, a plurality of wiring electrodes disposed on the base portion, and electrically connected to the plurality of transistors and the plurality of semiconductor light emitting devices, a partition wall disposed on the base portion, and formed to cover the plurality of transistors, and a connection electrode connecting some of the plurality of transistors and some of the plurality of wiring electrodes, wherein the connection electrode is configured to pass through the partition wall.

First claim

What is claimed is:

1. A display device, comprising:
a base portion;
a plurality of transistors disposed on the base portion;
a plurality of semiconductor light emitting devices disposed on the base portion;
a plurality of wiring electrodes disposed on the base portion, and electrically connected to the plurality of transistors and the plurality of semiconductor light emitting devices;
a planarization layer disposed on the base portion, and formed to cover the plurality of transistors; and
a connection electrode connecting some transistors of the plurality of transistors and some wiring electrodes of the plurality of wiring electrodes,
wherein the connection electrode is configured to pass through the planarization layer,
wherein the plurality of wiring electrodes comprises a VDD electrode and a VData electrode that are coplanar and interposed between the planarization layer and the base portion, and
wherein a distance separating the VDD electrode and the VData electrode is less than a width of the plurality of semiconductor light emitting devices.

2. The display device of claim 1 , wherein each of the some transistors and the some wiring electrodes is disposed on one surface of the planarization layer facing the base portion and located between opposite surfaces of the planarization layer.

3. The display device of claim 2 , wherein a part of the connection electrode is disposed on another surface of the planarization layer, and located between the opposite surfaces of the planarization layer.

4. The display device of claim 3 , wherein the one surface and the another surface are separated in a depth direction of the planarization layer, and the opposite surfaces are separated in a width direction of the planarization layer.

5. The display device of claim 3 , wherein the planarization layer comprises a plurality of via holes formed to pass through the planarization layer, and
wherein the part of the connection electrode is disposed inside the via hole.

6. The display device of claim 5 , wherein the via hole comprises:
a first via hole formed to overlap with the some transistors; and
a second via hole formed to overlap with the some wiring electrodes.

7. The display device of claim 6 , wherein the connection electrode comprises:
a first connection electrode disposed inside the first via hole;
a second connection electrode disposed inside the second via hole; and
a third connection electrode disposed on the another surface of the planarization layer to electrically connect the first and second connection electrodes.

8. The display device of claim 1 , wherein the planarization layer comprises a plurality of grooves formed to pass through the planarization layer, and
wherein the plurality of semiconductor light emitting devices are disposed inside the plurality of grooves.

9. The display device of claim 8 , wherein the some wiring electrodes comprise a protruding portion formed to protrude toward the plurality of grooves.

10. The display device of claim 9 , wherein the plurality of semiconductor light emitting devices are disposed to overlap with the protruding portion.

11. The display device of claim 10 , further comprising:
a dielectric layer formed between the some wiring electrodes and the plurality of semiconductor light emitting devices to maintain an insulation state between the some wiring electrodes and the plurality of semiconductor light emitting devices.

12. The display device of claim 11 , wherein the connection electrode is formed to pass through the planarization layer and the dielectric layer.

13. The display device of claim 8 , wherein another wiring electrode disposed in parallel to the some wiring electrodes comprises a protruding portion formed to protrude toward the plurality of grooves.

14. The display device of claim 9 , wherein the protruding portion of one of the some wiring electrodes is wider than another portion of the one of the some wiring electrodes.

15. The display device of claim 8 , wherein the plurality of grooves extend parallel to a surface of the base portion.

16. The display device of claim 1 , wherein the VDD electrode and the VData electrode comprise a first protruding portion and a second protruding portion formed to protrude into a groove, respectively.

17. The display device of claim 16 , wherein a semiconductor light emitting device from among the plurality of semiconductor light emitting device is disposed to overlap with both the first protruding portion and the second protruding portion.

18. A display device, comprising:
a base portion having a planar configuration;
a plurality of transistors disposed on the base portion;
a plurality of semiconductor light emitting devices disposed on the base portion;
a plurality of wiring electrodes disposed on the base portion, electrically connected to the plurality of transistors and the plurality of semiconductor light emitting devices, and including at least Vdd electrodes and Vdata electrodes,
wherein each of Vdd electrodes and Vdata electrodes includes a protruding portion that extends parallel to the base portion at a location of the plurality of semiconductor light emitting devices,
wherein a distance separating an adjacent pair of a Vdd electrode and a Vdata electrode from among the Vdd electrodes and the Vdata electrodes is less than a width of the plurality of semiconductor light emitting devices, and
wherein the adjacent pair of the Vdd electrode and the Vdata electrode are coplanar and interposed between a planarization layer and the base portion.

19. The display device of claim 18 , further comprising:
a connection electrode connecting some transistors of the plurality of transistors and some wiring electrodes of the plurality of wiring electrodes; and
a planarization layer disposed on the base portion, and formed to cover the plurality of transistors,
wherein the connection electrode is configured to pass through the planarization layer.

20. A display device, comprising:
a base portion;
a plurality of transistors disposed on the base portion;
a plurality of semiconductor light emitting devices disposed on the base portion;
a plurality of wiring electrodes disposed on the base portion, and electrically connected to the plurality of transistors and the plurality of semiconductor light emitting devices;
a planarization layer disposed on the base portion, and formed to cover the plurality of transistors; and
a connection electrode connecting some transistors of the plurality of transistors and some wiring electrodes of the plurality of wiring electrodes,
wherein the connection electrode is configured to pass through the planarization layer,
wherein the planarization layer comprises a plurality of grooves formed to pass through the planarization layer,
wherein the plurality of semiconductor light emitting devices are disposed inside the plurality of grooves,
wherein the some wiring electrodes comprise a protruding portion formed to protrude toward the plurality of grooves, and
wherein the plurality of semiconductor light emitting devices are disposed to vertically overlap with the protruding portion.

Assignees

• Lg Electronics Inc

Inventors

• Kim Soohyun
• Choi Wonseok
• Park Sungmin

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10H20/857 Primary

  Interconnections, e.g. lead-frames, bond wires or solder balls · CPC title

• H10H20/831

  characterised by their shape · CPC title

• H10H29/142 Primary

  Two-dimensional arrangements, e.g. asymmetric LED layout · CPC title