Substrate structure, package structure and method for manufacturing electronic package structure

Patent metadata

Field	Value
Publication number	US-11735433-B2
Application number	US-202117213033-A
Country	US
Kind code	B2
Filing date	Mar 25, 2021
Priority date	Mar 25, 2021
Publication date	Aug 22, 2023
Grant date	Aug 22, 2023

Abstract

A substrate structure, a package structure, and a method for manufacturing an electronic package structure provided. The substrate structure includes a dielectric layer, a trace layer, and at least one wettable flank. The dielectric layer has a first surface and a second surface opposite to the first surface. The trace layer is embedded in the dielectric layer and exposed from the first surface of the dielectric layer. The at least one wettable flank is stacked with a portion of the trace layer embedded in the dielectric layer.

First claim

What is claimed is:

1. A substrate structure, comprising:
a dielectric layer having a first surface and a second surface opposite to the first surface;
a trace layer embedded in the dielectric layer and exposed from the first surface of the dielectric layer;
at least one wettable flank stacked with a portion of the trace layer embedded in the dielectric layer; and
a protective layer covering a first surface of the at least one wettable flank.

2. The substrate structure of claim 1 , wherein the trace layer has a first surface exposed from the dielectric layer and a second surface opposite to the first surface, and the second surface of the trace layer is covered by the dielectric layer.

3. The substrate structure of claim 1 , wherein the at least one wettable flank is in contact with a first surface of the trace layer.

4. A substrate structure, comprising:
a dielectric layer having a first surface and a second surface opposite to the first surface;
a trace layer embedded in the dielectric layer and exposed from the first surface of the dielectric layer; and
at least one wettable flank stacked with a portion of the trace layer embedded in the dielectric layer;
wherein the at least one wettable flank is in contact with a first surface of the trace layer, and
wherein the at least one wettable flank has a curved corner proximal to the first surface of the trace layer.

5. The substrate structure of claim 1 , wherein the trace layer comprises a patterned metal layer between the at least one wettable flank and the dielectric layer.

6. The substrate structure of claim 1 , further comprising a patterned metal layer disposed on the second surface of the dielectric layer.

7. A substrate structure, comprising:
a dielectric layer having a first surface and a second surface opposite to the first surface;
a trace layer embedded in the dielectric layer and exposed from the first surface of the dielectric layer;
at least one wettable flank stacked with a portion of the trace layer embedded in the dielectric layer; and
a patterned metal layer disposed on the second surface of the dielectric layer,
wherein the patterned metal layer comprises an antenna structure.

8. The substrate structure of claim 1 , further comprising a conductive via passing through the dielectric layer and connected to the trace layer.

9. The substrate structure of claim 8 , wherein the conductive via and a portion of the trace layer form a shielding structure.

10. The substrate structure of claim 1 , wherein the at least one wettable flank comprises rolled metal grains.

11. A package structure, comprising:
a dielectric layer having a first surface and a second surface opposite to the first surface;
a trace layer proximal to the first surface of the dielectric layer;
at least one wettable flank on a first side of the dielectric layer;
a die on the first side of the dielectric layer; and
an antenna structure on the second surface of the dielectric layer.

12. The package structure of claim 11 , wherein the trace layer is embedded in the dielectric layer and exposed from the first surface of the dielectric layer.

13. The package structure of claim 11 , wherein the at least one wettable flank is disposed on the first surface of the dielectric layer.

14. The package structure of claim 11 , wherein the at least one wettable flank comprises at least two wettable flanks, the at least two wettable flanks and the dielectric layer define a space, and the die is disposed in the space.

15. The package structure of claim 11 , wherein a thickness of the die is equal to or less than a thickness of the at least one wettable flank.

16. The substrate structure of claim 1 , wherein the at least one wettable flank comprises at least two wettable flanks, and the first surfaces of the at least two wettable flanks facing away from the first surface of the dielectric layer are substantially coplanar.

17. A substrate structure, comprising:
a dielectric layer having a first surface and a second surface opposite to the first surface;
a trace layer embedded in the dielectric layer and exposed from the first surface of the dielectric layer; and
at least one wettable flank stacked with a portion of the trace layer embedded in the dielectric layer;
wherein the at least one wettable flank comprises at least two wettable flanks, and the first surfaces of at least two wettable flanks facing away from the first surface of the dielectric layer are substantially coplanar, and
wherein the trace layer comprises a barrier layer exposed from the first surface of the dielectric layer.

18. The substrate structure of claim 17 , wherein the wettable flank has a curved corner in contact with the barrier layer.

Assignees

• Advanced Semiconductor Eng

Inventors

• Yen You-Lung
• Appelt Bernd Karl

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W70/6875

  being on a metallic substrate, e.g. insulated metal substrates [IMS] · CPC title

• H10W44/248

  for antennas · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title