Cascade communications between FPGA tiles

Patent metadata

Field	Value
Publication number	US-11734216-B2
Application number	US-202217675549-A
Country	US
Kind code	B2
Filing date	Feb 18, 2022
Priority date	Oct 18, 2019
Publication date	Aug 22, 2023
Grant date	Aug 22, 2023

Abstract

A tile of an FPGA provides memory, arithmetic functions, or both. Connections directly between multiple instances of the tile are available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic and memory circuits are increased, operand sizes are increased, or both. By using the cascade connections, multiple tiles can be used together as a single, larger tile. Thus, implementations that need memories of different sizes, arithmetic functions operating on different sized operands, or both, can use the same FPGA without additional programming or waste. Using cascade communications, more tiles are used when a large memory is needed and fewer tiles are used when a small memory is needed and the waste is avoided.

First claim

What is claimed is:

1. A circuit comprising:
a first tile of a field programmable gate array (FPGA) comprising a first multiply and accumulate (MAC) circuit and a first memory circuit, the first memory circuit coupled to a connection fabric of the FPGA to receive a read address, an input block address, and a mask, the first memory circuit configured to:
generate a modified block address based on a block address of the first memory circuit and the mask; and
access data based on the modified block address matching the input block address; and
a second tile of the FPGA comprising a second MAC circuit and a second memory circuit, the first memory circuit coupled to the second memory circuit by a communication connection that does not use the connection fabric to receive the read address from the first tile.

2. The circuit of claim 1 , wherein:
the second memory circuit of the second tile of the FPGA is configured to store data received via the communication connection.

3. The circuit of claim 2 , wherein:
the second memory circuit of the second tile of the FPGA is configured to simultaneously perform a first operation and a second operation, the first operation providing first data to the second MAC circuit of the second tile of the FPGA, the second operation storing the data received via the communication connection with the first tile.

4. The circuit of claim 2 , wherein the second memory circuit is configured to provide a first set of outputs to a third tile of the FPGA via a second communication connection that does not use the connection fabric.

5. The circuit of claim 1 , wherein a bit of the read address indicates whether to provide data from the first memory circuit or the second memory circuit.

6. The circuit of claim 1 , wherein data is provided from both the first memory circuit and the second memory circuit based on the read address.

7. The circuit of claim 1 , wherein:
in response to a configuration signal, the second MAC circuit is configured to receive a second set of inputs via a second communication connection that does not use the connection fabric from the first tile of the FPGA.

8. The circuit of claim 1 , wherein the second MAC circuit is further configured to provide a first set of outputs to a third tile of the FPGA via a second communication connection that does not use the connection fabric.

9. A method comprising:
receiving, by a first tile of a field programmable gate array (FPGA) comprising a first multiply and accumulate (MAC) circuit and a first memory circuit, from a connection fabric of the FPGA, a read address, an input block address, and a mask;
generating, by the first tile, a modified block address based on a block address of the first memory circuit and the mask;
accessing, based on the modified block address matching the input block address, data; and
transmitting, by the first tile of the FPGA to a second tile of the FPGA comprising a second MAC circuit and a second memory circuit, the read address via a communication connection that does not use the connection fabric.

10. The method of claim 9 , further comprising:
storing, by the second memory circuit of the second tile of the FPGA, data received via the communication connection.

11. The method of claim 10 , further comprising:
simultaneously performing, by the second memory circuit of the second tile of the FPGA, a first operation and a second operation, the first operation providing first data to the second MAC circuit of the second tile of the FPGA, the second operation storing the data received via the communication connection.

12. The method of claim 9 , further comprising:
providing, by the second memory circuit, a first set of outputs to a third tile of the FPGA via a second communication connection that does not use the connection fabric.

13. The method of claim 9 , wherein a bit of the read address indicates whether to provide data from the first memory circuit or the second memory circuit.

14. The method of claim 9 , wherein data is provided from both the first memory circuit and the second memory circuit based on the read address.

15. A non-transitory machine-readable storage medium containing instructions that, when executed by one or more processors, cause the one or more processors to control configuration of a field programmable gate array (FPGA) comprising:
a first tile comprising a first multiply and accumulate (MAC) circuit and a first memory circuit, the first memory circuit coupled to a connection fabric of the FPGA to receive a read address, an input block address, and a mask, the first memory circuit configured to:
generate a modified block address based on a block address of the first memory circuit and the mask; and
access data based on the modified block address matching the input block address; and

a second tile comprising a second MAC circuit and a second memory circuit, the first memory circuit coupled to the second memory circuit by a communication connection that does not use the connection fabric to receive the read address from the first tile.

16. The non-transitory machine-readable storage medium of claim 15 , wherein:
the second memory circuit of the second tile of the FPGA is configured to store data received via the communication connection.

17. The non-transitory machine-readable storage medium of claim 16 , wherein:
the second memory circuit of the second tile of the FPGA is configured to simultaneously perform a first operation and a second operation, the first operation providing first data to the second MAC circuit of the second tile of the FPGA, the second operation storing the data received via the communication connection.

18. The non-transitory machine-readable storage medium of claim 16 , wherein the second memory circuit is configured to provide a first set of outputs to a third tile of the FPGA via a second communication connection that does not use the connection fabric.

19. The non-transitory machine-readable storage medium of claim 15 , wherein a bit of the read address indicates whether to provide data from the first memory circuit or the second memory circuit.

20. The non-transitory machine-readable storage medium of claim 15 , wherein data is provided from both the first memory circuit and the second memory circuit based on the read address.

Assignees

• Achronix Semiconductor Corp

Inventors

• Pugh Daniel
• Nijssen Raymond
• Fitton Michael Philip
• Van Der Goot Marcel

Classifications

• G06F15/7867

  with reconfigurable architecture · CPC title

• G06F13/4027 Primary

  using bus bridges (G06F13/4022 takes precedence) · CPC title